Appendix A: Signal Concordance

Every netlist gate named in this book — 1019 signals — with its role, cell type, and the chapter that owns its primary description. Gate names come from the DMG-CPU B netlist via msinger/dmg-schematics; each is independently checkable against the schematics and the dmg-sim Verilog. Roles are taken from the owning chapter's reference blocks; gates without a role row appear in prose or chain descriptions, where the linked chapter carries the context.

This index is generated from the book's own text and validated against the netlist sources, so every entry corresponds to a real cell and a real mention.

Gate	Role	Type	Primary chapter	Also appears in
ABAF			Mode Transitions
ABAK	Per-slot-reset shared gating term	or2	Mode 2: OAM Scan	Mode Transitions
ABEZ			Mode Transitions
ABON	FAMU enable	not_x2 chain	Mode 3: The Sprite Pipeline
ACOR	Wave data latch reset driver (= NOT(`apu_reset`))	not_x1	CH3: Wave Channel
ACYL			OAM DMA
ADAR			Register Writes
ADEH	ATAL complement	not_x1	The Clock Tree	Register Writes
ADYK	Phase generator ring stage 4	dff	The Clock Tree	Register Writes
AFAS	Ring decode driving CUPA (inputs ADAR, ATYP)	nor2	Register Writes
AFUR	Phase generator ring stage 1	dff	The Clock Tree	Register Writes
AGET	Length counter load enable (upper bits)	not_x1	Length Counters and Power Cycling
AJEP			OAM DMA
AJER	CH1 prescaler /2 stage 1	dffr	APU Clock Tree and Frame Sequencer	CH1/CH2: Pulse Channels, Sweep and Envelope
AJON	Mode 3 + non-DMA	and2	Rendering Mode Control	OAM and VRAM Access, OAM DMA, CPU-Visible Mode Boundaries
AJUJ	OAM-access permit	nor3	OAM and VRAM Access	OAM DMA, CPU-Visible Mode Boundaries
AKYD	CH2 length counter bit 5 (MSB)	tffnl	Length Counters and Power Cycling
ALEF	Phase generator ring stage 2	dff	The Clock Tree	Register Writes
ALES			Mode Transitions
ALET	4 MHz PPU main clock	not_x2	The Clock Tree	Rendering Mode Control, Register Writes, Register Reads
AMAB	OAM CPU-write address gate	and2	OAM and VRAM Access
AMUV	LCDC.3 → ~ma10 tri-state driver	not_if0	Mode 3: The BG Pipeline
AMYG			Mode 2: OAM Scan
ANEL	Scan counter reset chain stage 2	dffr	OAM DMA	Mode 2: OAM Scan, Mode Transitions
ANOM	Scan counter reset	nor2	Mode 2: OAM Scan	Mode Transitions
ANOS	Crystal feedback NAND	nand2	The Clock Tree
ANYP	SCY read enable (AND2 with `ppu_rd`)	and2	Register Reads
APAR			OAM DMA	Mode 2: OAM Scan
APOV	CUPA driver stage 4	not	Register Writes
APUG			The IF Register
APUK	Phase generator ring stage 3	dff	The Clock Tree	Register Writes
APUV	CH1 prescaler clock buffer	not_x1	APU Clock Tree and Frame Sequencer
AREV	CUPA driver stage 5	nand2	Register Writes
AROR	Sprite-trigger gate (LCDC.1-gated rendering enable)	and2	LCDC Structure	Mode 2: OAM Scan, Mode 3: The BG Pipeline, Mode 3: The Sprite Pipeline
AROV			Register Writes
ARUR	SCX write enable	and2	Register Writes
ASAM	OAM CPU-address disable	or3	Rendering Mode Control	OAM DMA
ASEN	BESU reset driver	or2	Rendering Mode Control	Mode 2: OAM Scan, Mode Transitions
ATAG	APU 4 MHz polarity restore	not_x1	APU Clock Tree and Frame Sequencer
ATAL	4 MHz buffered enable	not_x2	The Clock Tree	Register Writes
ATAR	VID_RST active-high	not	Rendering Mode Control	Mode 2: OAM Scan, Mode Transitions
ATEJ			Rendering Mode Control	Mode 2: OAM Scan, Mode 3: The BG Pipeline, Mode 3: The Sprite Pipeline
ATEP	CH2 prescaler /2 stage 1	dffr	APU Clock Tree and Frame Sequencer	CH1/CH2: Pulse Channels
ATYP			Register Writes
AVAP	Mode 2→3 trigger	not_x2	Mode 2: OAM Scan	The Clock Tree, Rendering Mode Control, Register Writes, Register Reads
AVER	= NAND2(mode2, XYSO) — scan-phase term in BYCU	nand2	OAM DMA	Mode 2: OAM Scan, OAM and VRAM Access
AVET	Crystal feedback NAND	nand2	The Clock Tree
AVOG	SCX read enable (AND2 with `ppu_rd`)	and2	Register Reads
AWOH			Mode Transitions
AXAD			Mode 3: The BG Pipeline
AZEG	CH2 prescaler clock buffer	not_x1	APU Clock Tree and Frame Sequencer
AZEM	AROR second input (rendering-active AND mid-scanline-control)	and2	Rendering Mode Control	Mode 2: OAM Scan
AZET	Wave-RAM precharge-window term (with AZUS)	dffr	CH3: Wave Channel
AZOF	PPU clock buffer	not_x6	The Clock Tree	APU Clock Tree and Frame Sequencer
AZUS	wave_data_latch synchroniser stage 3	dffr	CH3: Wave Channel
AZYB	Slot counter reset driver	not_x1	Mode 2: OAM Scan	Mode Transitions
BAFU	apu_wr buffer stage 1	not_x1	APU Clock Tree and Frame Sequencer
BAFY	AMUV enable (BG tilemap stage)	not_x2	Mode 3: The BG Pipeline
BAGY	BYBA/DOBA reset driver	not_x1	Mode 2: OAM Scan
BALU	OAM-parse reset (active-high)	not_x1	Mode 2: OAM Scan	Mode Transitions
BAMA	wave_data_latch synchroniser reset driver (= NOT(`apu_reset`))	not_x1	CH3: Wave Channel
BANO	wave_data_latch synchroniser stage 2	dffr	CH3: Wave Channel
BAPY			Register Writes
BARY	CH3 DAC input bit 0 gate (AND with `ch3_active`)	and2	CH3: Wave Channel
BATU			The IF Register
BAVE	Sweep pace = 0 detector	and3	Sweep and Envelope
BAVU	`ch4_1mhz` — CH4 base clock (`= NOT avok`, ~1.048 MHz)	not_x1	CH4: Noise Channel
BAXO			Mode 3: The Sprite Pipeline
BEBA	= NOT(AVOG) — SCX read drivers' `ena_n`	not_x1	Register Reads
BEBU	Scan-complete aggregate	or3	The Clock Tree	Rendering Mode Control, Mode 2: OAM Scan, Mode Transitions
BEDY	SCY write enable	and2	Register Writes
BEGO	Slot counter bit 2	dffr	Mode 2: OAM Scan
BEGU	Wave data latch bit 3	drlatch_ee	CH3: Wave Channel
BELU	`data_phase` gate (= NOR2(ATYP, `clk_ena_n`))	nor2	Register Reads
BELY	CH3 DAC input bit 3 gate (AND with `ch3_active`)	and2	CH3: Wave Channel
BEPA	Wave data latch bit 7	drlatch_ee	CH3: Wave Channel
BERU			Register Writes
BESE	Slot counter bits 0–3	dffr (toggle)	Mode 2: OAM Scan
BESU	Scan-active latch (Q=1 during Mode 2)	nor_latch	Rendering Mode Control	Register Writes, Register Reads, OAM and VRAM Access
BETE			OAM DMA
BEVA	`data_phase` rebuffer	not_x6	Register Reads
BEXA	Sweep-fire latch	dffr	Sweep and Envelope
BODE			OAM DMA
BOGA	PPU timing divider (held 0 under VID_RST)		Register Writes	Post-Boot State
BOGE			OAM and VRAM Access	OAM DMA, Mode 2: OAM Scan
BONE	Sweep overflow channel-disable term (= NOT(`ch1_sum_ovfl_n`))	not_x1	Sweep and Envelope
BOPA	CH3 DAC input bit 2 gate (AND with `ch3_active`)	and2	CH3: Wave Channel
BORA	Wave data latch bit 6	drlatch_ee	CH3: Wave Channel
BUDY	Wave data latch bit 2	drlatch_ee	CH3: Wave Channel
BUKO	Length counter bit-3→4 ripple inverter	not_x1	Length Counters and Power Cycling
BURE	Frame-sequencer 512 Hz clock	not_x2	APU Clock Tree and Frame Sequencer
BURY	BEXA async-reset driver (pace 0)	nor2	Sweep and Envelope
BUSA	wave_data_latch synchroniser stage 1	dffr	CH3: Wave Channel
BUVA	CH2 length counter bit 4	tffnl	Length Counters and Power Cycling
BUWY	= NOT(ANYP) — SCY read drivers' `ena_n`	not_x1	Register Reads
BUZA			Rendering Mode Control
BYBA	Scan-done flag	dffr	The Clock Tree	Mode 2: OAM Scan, Mode 3: The BG Pipeline, Mode Transitions
BYCU	= NAND3(CUFE, XUJY, AVER) — COTA driver	nand3	OAM DMA	Mode 2: OAM Scan, OAM and VRAM Access
BYHA			Mode Transitions
BYJO	AZEM first input (mid-scanline control)	not_x1	Mode 2: OAM Scan
BYKA	CH3 DAC input bit 1 gate (AND with `ch3_active`)	and2	CH3: Wave Channel
BYLU	Frame sequencer /2 → 128 Hz (sweep tap)	dffr	APU Clock Tree and Frame Sequencer	Post-Boot State
BYMO	Length counter load enable (lower bits)	not_x1	Length Counters and Power Cycling
BYRA	Sweep shift-step counter bit 2	tffnl	Sweep and Envelope
BYRY	`data_phase` inverter (of BELU)	not_x2	Register Reads
CAGY	CH2 duty counter bit 1	dffr_cc	CH1/CH2: Pulse Channels
CAJA	Sweep shift-step counter bit 1	tffnl	Sweep and Envelope
CAKE			Mode 2: OAM Scan
CALA	CH1 overflow detector (NOT stage)	not_x1	CH1/CH2: Pulse Channels
CALO	CH1 prescaler /2 stage 2	dffr	APU Clock Tree and Frame Sequencer	CH1/CH2: Pulse Channels
CALY	int_serial driver (toggle DFF on serial transfer clock)	dffr	The IF Register
CAMA	CH2 divider toggle clock (NOR stage)	nor2	CH1/CH2: Pulse Channels
CAME	CH2 length counter bit 3	tffnl	Length Counters and Power Cycling
CANO	CH2 duty counter bit 0 (LSB)	dffr	CH1/CH2: Pulse Channels
CAPE			Mode 2: OAM Scan
CAPY	CH1 length-clock gate	nor3	Length Counters and Power Cycling
CARE	Global sprite-save enable	and3	Mode 2: OAM Scan	Mode Transitions, Scanline and Frame Timing
CARU	Frame sequencer /2 → 256 Hz (length tap)	dffr	APU Clock Tree and Frame Sequencer	Length Counters and Power Cycling, Post-Boot State
CARY	`noise_counter_clk` — CH4 shift-divider clock (`ch4_1mhz & gary`)	and2	CH4: Noise Channel
CASY	SCX bit-7 read driver	not_if0	Register Reads
CATA	SCX bit-5 read driver	not_if0	Register Reads
CATU	Scan-boundary trigger	dffr	OAM DMA	Mode 2: OAM Scan, Mode Transitions, CPU-Visible Mode Boundaries
CAVA	CH1 duty-pattern select	nor2	CH1/CH2: Pulse Channels
CAXO	CH1 duty-pattern select	nor2	CH1/CH2: Pulse Channels
CAXU			Mode 2: OAM Scan
CAXY	Sweep counter bit 2	tffnl	Sweep and Envelope
CEDE	inverted `dma_addr_ext`	not_x2	OAM DMA
CEDU	SCX bit-4 read driver	not_if0	Register Reads
CEDY			Mode 2: OAM Scan	Mode 3: The Sprite Pipeline
CEHA			Mode 2: OAM Scan
CEMO	CH2 prescaler /2 stage 2	dffr	APU Clock Tree and Frame Sequencer	CH1/CH2: Pulse Channels
CENO	XUPY-phased scan-active copy	dffr	The Clock Tree	Rendering Mode Control, Mode 2: OAM Scan, Races
CERA	CH2 length counter bit 1	tffnl	Length Counters and Power Cycling
CERY	CH3 prescaler /2 stage	dffr	APU Clock Tree and Frame Sequencer	CH3: Wave Channel
CESY	Wave data latch bit 1	drlatch_ee	CH3: Wave Channel
CEVO	Wave data latch bit 5	drlatch_ee	CH3: Wave Channel
CEVU	CH1 duty-pattern select	nor2	CH1/CH2: Pulse Channels
CEXO	CH4 shift divider bit 0	dffr	CH4: Noise Channel
CODO	CH1 duty counter-state decode	not_x1	CH1/CH2: Pulse Channels
COMY	CH1 overflow capture (/2 toggle)	dffr	CH1/CH2: Pulse Channels
CONU	CH2 length counter bit 2	tffnl	Length Counters and Power Cycling
COPA	Sweep shift-step counter bit 0	tffnl	Sweep and Envelope
COPU	CH1 divider bit 10 (MSB)	tffnl	CH1/CH2: Pulse Channels
COSO	CH1 duty-pattern select	nor2	CH1/CH2: Pulse Channels
COTA	Stage-2 capture enable; complement WOVU drives the OAM bitline precharge	not_x1	OAM DMA	Mode 2: OAM Scan, OAM and VRAM Access
COWE	CH1 PWM gated by channel-running	and2	CH1/CH2: Pulse Channels
COZE	Sweep counter-at-max detector	and3	Sweep and Envelope
CUFE	= OAI21(FEXX, `dma_run`, `dma_phi_n`) — $FExx/DMA bus-cycle term in BYCU	oai21	OAM DMA	Mode 2: OAM Scan, OAM and VRAM Access
CUGA	SCX bit-2 read driver	not_if0	Register Reads
CULE	CH2 duty counter clock	not_x1	CH1/CH2: Pulse Channels
CUPA	Shared PPU register write strobe	combinational (derived from phase gen)	Register Writes	Register Reads, OAM and VRAM Access, Mode 2: OAM Scan
CUPO	Sweep counter bit 0	tffnl	Sweep and Envelope
CUSA	SCY bit-4 read driver	not_if0	Register Reads
CUVO	Wave data latch bit 4	drlatch_ee	CH3: Wave Channel
CUXY	Slot counter bit 1	dffr	Mode 2: OAM Scan
CYBO	CH3 prescaler clock buffer	not_x1	APU Clock Tree and Frame Sequencer
CYFO	Wave data latch bit 0	drlatch_ee	CH3: Wave Channel
CYKE			Mode 2: OAM Scan
CYMU	Sweep counter load enable (NOT stage)	not_x1	Sweep and Envelope
CYPU	Sweep counter bit 1	tffnl	Sweep and Envelope
CYRA			OAM DMA	Mode 2: OAM Scan
CYRE	CH2 length-clock gate (DEME) input	dffr	Length Counters and Power Cycling
CYSE	CH2 PWM gated by channel-running	and2	CH1/CH2: Pulse Channels
CYVO	CH2 divider bit 3	tffnl	CH1/CH2: Pulse Channels
DAFA	Sweep counter load enable (NOR stage)	nor2	Sweep and Envelope
DAJO	CH1 duty counter clock	not_x1	CH1/CH2: Pulse Channels
DALE	CH4 shift divider bit 5	dffr	CH4: Noise Channel
DAPE	CH1 duty counter bit 2 (MSB)	dffr_cc	CH1/CH2: Pulse Channels
DARE	CH2 duty counter-state decode	not_x1	CH1/CH2: Pulse Channels
DARY	CH4 divider low-tap mux (bits 0,1,2,3 group)	ao2222	CH4: Noise Channel
DASA			Mode 2: OAM Scan
DATO	CH4 LFSR output → envelope gate	or2	CH4: Noise Channel
DEGO	Per-slot X match, FEFY group (active-low)	nand3	Mode 3: The Sprite Pipeline
DEKO	CH4 shift divider bit 1	dffr	CH4: Noise Channel
DEME	CH2 length-clock gate	nor3	Length Counters and Power Cycling
DEMO	CH4 shift divider bit 7	dffr	CH4: Noise Channel
DEPO	OAM attribute bit 7 latch (BG-over-OBJ priority)	dlatch_ee	Mode 3: The Sprite Pipeline
DERE	CH4 shift divider bit 12	dffr	CH4: Noise Channel
DERO	CH3 wave-position counter clock	not_x1	CH3: Wave Channel
DERU	CH1 divider ripple inverter (bits 8–10)	not_x1	CH1/CH2: Pulse Channels
DETE	CH4 shift divider bit 9	dffr	CH4: Noise Channel
DOBA	ALET-clocked scan-done-prev	dffr	The Clock Tree	Mode 2: OAM Scan, Mode Transitions, Scanline and Frame Timing
DOCA	CH2 divider toggle clock (NOT stage)	not_x1	CH1/CH2: Pulse Channels
DODA	CH3 length-clock gate	nor3	Length Counters and Power Cycling
DOJU	CH2 duty-pattern select	nor2	CH1/CH2: Pulse Channels
DOKA	Overflow-capture self-clear term (= AND2(COMY, `ch1_1mhz`))	and2	CH1/CH2: Pulse Channels
DOKE	CH4 shift divider bit 6	dffr	CH4: Noise Channel
DOME	CH2 PWM latch	dffr	CH1/CH2: Pulse Channels
DOMO	CH2 duty-pattern select	nor2	CH1/CH2: Pulse Channels
DONE	CH2 divider bit 0	tffnl	CH1/CH2: Pulse Channels
DOSE	CH4 shift divider bit 8	dffr	CH4: Noise Channel
DOTA	CH4 shift divider bit 11	dffr	CH4: Noise Channel
DOVE	CH2 duty-pattern select	nor2	CH1/CH2: Pulse Channels
DOXE	SCX bit-6 read driver	not_if0	Register Reads
DUGA			OAM DMA
DUJU	CH2 divider load enable	nor2	CH1/CH2: Pulse Channels
DURE	CH4 shift divider bit 4	dffr	CH4: Noise Channel
DUWO	CH1 PWM latch	dffr	CH1/CH2: Pulse Channels
DYBA	= NOT(BYVA) — per-slot line-reset term	not_x1	Mode 3: The Sprite Pipeline
DYBE	Slot counter bit 3 (MSB)	dffr	Mode 2: OAM Scan
DYDU	Per-slot X match, FEFY group (active-low)	nand3	Mode 3: The Sprite Pipeline
DYKA	Per-slot X match, FOVE group (active-low)	nand3	Mode 3: The Sprite Pipeline
DYKY	CUPA driver stage 1	not	Register Writes
DYMU	CH2 duty counter-state decode	and2	CH1/CH2: Pulse Channels
DYNU	CH2 divider bit 1	tffnl	CH1/CH2: Pulse Channels
DYRO	Gated 256 Hz length tick (= NOT(DEME))	not_x1	Length Counters and Power Cycling
DYRU	COMY async-reset driver (= NOR(`apu_reset`, `ch1_restart`, DOKA))	nor3	CH1/CH2: Pulse Channels
DYTA	CH2 duty-pattern select	nor2	CH1/CH2: Pulse Channels
DYVE	CH2 duty counter bit 2 (MSB)	dffr_cc	CH1/CH2: Pulse Channels
DYWE	Slot-0 reset driver = OR2(DYBA, EBOJ)	or2	Mode 3: The Sprite Pipeline
EBEB	Slot-3 write-enable inverter	not_x1	Mode 2: OAM Scan	Races
EBOJ	Slot-0 fetch-done flag (d = GUVA, clk = WUTY)	dffr	Mode 3: The Sprite Pipeline	Mode 2: OAM Scan
EBOS			Mode 2: OAM Scan
ECED			OAM DMA	Mode 2: OAM Scan, Mode 3: The Sprite Pipeline
EDOS	SCX bit-0 read driver	not_if0	Register Reads
EFAL	CH3 wave-position bit 4 (MSB)	dffr	CH3: Wave Channel
EFAR	CH3 wave-position bit 0 (`wave_nibble_sel`)	dffr	CH3: Wave Channel
EFUZ	CH3 wave-position bit 2	dffr	CH3: Wave Channel
EFYL	Per-slot X match, FOVE group (active-low)	nand3	Mode 3: The Sprite Pipeline
EGOG	CH2 duty counter-state decode	and2	CH1/CH2: Pulse Channels
EGOM	Per-slot X match, FOVE group (active-low)	nand3	Mode 3: The Sprite Pipeline
EKOB	SCX bit-1 read driver	not_if0	Register Reads
EKOV	CH1 divider bit 7	tffnl	CH1/CH2: Pulse Channels
ELYN	Scan counter bit 3	dffr	Mode 2: OAM Scan
ELYX	CH4 divider mid-tap mux (bits 4,5,6,7 group)	ao2222	CH4: Noise Channel
EMUS	CH1 divider bit 8	tffnl	CH1/CH2: Pulse Channels
EMYR	Volume saturation detector (vol 0 + down)	nor5	Sweep and Envelope
ENEF	Y-compare carry-chain bit 1	full_add	Mode 2: OAM Scan
ENEK	CH1 duty counter-state decode	and2	CH1/CH2: Pulse Channels
EPOR	CH4 shift divider bit 3	dffr	CH4: Noise Channel
EPYK	CH1 divider load enable	nor2	CH1/CH2: Pulse Channels
EROS	CH1 duty counter bit 1	dffr_cc	CH1/CH2: Pulse Channels
ERUC	Y-compare carry-chain bit 0	full_add	Mode 2: OAM Scan
ERUS	CH3 wave-position bit 1	dffr	CH3: Wave Channel
ERUT	CH4 shift divider bit 10	dffr	CH4: Noise Channel
ERYC	CH2 length counter bit 0	tffnl	Length Counters and Power Cycling
ERYF	CH4 divider low-tap aggregate	or2	CH4: Noise Channel
ESEP	CH4 shift divider bit 13	dffr	CH4: Noise Channel
ESUT	CH1 duty counter bit 0 (LSB)	dffr	CH1/CH2: Pulse Channels
ETAN	Wave-position counter reset (active-low)	nor2	CH3: Wave Channel
ETYR	CH4 divider high-tap mux (bits 8–13)	ao222222	CH4: Noise Channel
EVAK	CH1 divider bit 9	tffnl	CH1/CH2: Pulse Channels
EXEL	CH3 wave-position bit 3	dffr	CH3: Wave Channel
EZEF	CH4 shift divider bit 2	dffr	CH4: Noise Channel
EZOF	CH2 divider bit 2	tffnl	CH1/CH2: Pulse Channels
EZOZ	CH1 duty counter-state decode	and2	CH1/CH2: Pulse Channels
EZUL	CH4 LFSR-output / bypass mux	mux	CH4: Noise Channel
FABO	`ch3_restart` sample clock (= NOT(`ch3_2mhz`))	not_x1	CH3: Wave Channel
FAHA	Scan counter bit 4	dffr	Mode 2: OAM Scan
FAJU	`ch3_fdis` enable pulse (= NOT(GYRA))	not_x1	CH3: Wave Channel
FAMU	`~ma4` tri-state driver	not_if0	Mode 3: The Sprite Pipeline
FECO	Y-compare carry-chain bit 2	full_add	Mode 2: OAM Scan
FEFY	Sprites 0–4 X-match aggregate	nand5	Mode 2: OAM Scan	Mode 3: The BG Pipeline, Mode 3: The Sprite Pipeline
FEME	CH4 LFSR shift-clock select (`ff22_d7 ? etyr : eryf`)	mux	CH4: Noise Channel
FEMO			Mode 2: OAM Scan
FENA	Volume counter bit 3	tffnl	Sweep and Envelope
FENO	Volume counter bit 0	tffnl	Sweep and Envelope
FEPO	Sprite X priority aggregate	or2	Rendering Mode Control	Mode 2: OAM Scan, Mode 3: The BG Pipeline, Mode 3: The Sprite Pipeline
FEPU			Mode 2: OAM Scan
FETE	Volume counter bit 1	tffnl	Sweep and Envelope
FETO	Scan-done decode	and4	Mode 2: OAM Scan	Mode Transitions
FETY	CH3 counter-wrap interlock (/2 toggle)	dffr	CH3: Wave Channel
FEVA	CH1 divider bit 6	tffnl	CH1/CH2: Pulse Channels
FEXX	$FExx address-range decode (= NOT(ROPE))	not_x2	OAM and VRAM Access
FFFF			Interrupt Dispatch
FOBA	NR34 trigger M-cycle synchroniser	dffr	CH3: Wave Channel
FOCO	Slot-3 selector	nand4	Mode 2: OAM Scan
FOFA			Mode 2: OAM Scan
FOMY	Volume counter bit 2	tffnl	Sweep and Envelope
FONE			Mode 2: OAM Scan
FONO			Mode 2: OAM Scan	Mode 3: The Sprite Pipeline
FONY	Scan counter bit 5 (MSB)	dffr	Mode 2: OAM Scan
FOVE	Sprites 5–9 X-match aggregate	nand5	Mode 2: OAM Scan	Mode 3: The BG Pipeline, Mode 3: The Sprite Pipeline
FOZU	CH3 active-bit nor_latch	nor_latch	CH3: Wave Channel
FUFO	XYMO complement	not_x1	Mode 3: The Sprite Pipeline
FUKY			Mode 2: OAM Scan
FULO	CH1 divider toggle clock (NOR stage)	nor2	CH1/CH2: Pulse Channels
FUVE			Mode 2: OAM Scan
FUVO	`ch3_fdis` disable level (= NOR(`ch3_amp_en_n`, `apu_reset`))	nor2	CH3: Wave Channel
FUWA	Y-compare carry-chain bit 5	full_add	Mode 2: OAM Scan
FUXO	CH2 divider bit 4	tffnl	CH1/CH2: Pulse Channels
FUXU	Slot-0 X save strobe (store-counter = 0 decode)	not_x1	Mode 3: The Sprite Pipeline
FYCU			Mode 2: OAM Scan
FYGO	FOZU clear term (= OR3(`apu_reset`, GEDO, `ch3_amp_en_n`))	or3	CH3: Wave Channel
FYNE	`horu_512hz` buffer chain stage	not_x3	APU Clock Tree and Frame Sequencer
FYRE	Volume saturation detector (vol 15 + up)	not_x1	Sweep and Envelope
GACE	NOT(GOPU) — Y-compare sum bit 4, complemented	not_x1	Mode 2: OAM Scan
GALE	`horu_512hz` buffer chain stage	mux	APU Clock Tree and Frame Sequencer
GAME	`lfsr_out` — CH4 LFSR output AND `ch4_active`	and2	CH4: Noise Channel
GANE	CH2 divider bit 7	tffnl	CH1/CH2: Pulse Channels
GANO	CH2 divider bit 5	tffnl	CH1/CH2: Pulse Channels
GARA	`ch3_restart` synchroniser DFF	dffr	CH3: Wave Channel
GARY	CH4 shift-divider clock-enable latch (cleared by trigger)	dffr	CH4: Noise Channel
GAVA	Scan counter clock	or2	Mode 2: OAM Scan
GAVU	NR34 trigger-bit capture	drlatch_ee	CH3: Wave Channel
GAXE	CH1 divider bit 0	tffnl	CH1/CH2: Pulse Channels
GEDO	CH3 length-stop term (length expired AND NR34 length enable)	and2	CH3: Wave Channel
GEJY	OBJ_SIZE mux	ao22	LCDC Structure	Mode 3: The Sprite Pipeline
GEKU	CH1 divider toggle clock (NOT stage)	not_x1	CH1/CH2: Pulse Channels
GENA	`ch4_active` nor_latch (set by `ch4_restart`)	nor_latch	CH4: Noise Channel
GEPO	CH4 LFSR-reset OR (`ch4_restart`, `apu_reset`)	or2	CH4: Noise Channel
GEPY	CH4 length-clock gate	nor3	Length Counters and Power Cycling
GESE	`sprite_y_match` driver	not_x1	Mode 2: OAM Scan
GEWY	NOT(WUHU) — Y-compare sum bit 7, complemented	not_x1	Mode 2: OAM Scan
GEXY	`horu_512hz` buffer chain stage	not_x1	APU Clock Tree and Frame Sequencer
GOBA	SCY bit-1 read driver	not_if0	Register Reads
GOCA	CH2 divider bit 6	tffnl	CH1/CH2: Pulse Channels
GODO	SCY bit-3 read driver	not_if0	Register Reads
GOFU	CH4 prescaler load-enable NOR (`ch4_restart`, `gary`)	nor2	CH4: Noise Channel
GOFY	NR34 trigger nor_latch (q_n is held)	nor_latch	CH3: Wave Channel
GOGE	CH4 LFSR reset (`= NOT gepo`)	not_x2	CH4: Noise Channel
GOJU	Y-compare carry-chain bit 6	full_add	Mode 2: OAM Scan
GOMO			Mode 3: The Sprite Pipeline
GONE	`ch4_restart` synchroniser DFF (clk `hama_512khz`)	dffr	CH4: Noise Channel
GONU	SCY bit-2 read driver	not_if0	Register Reads
GOPU	Y-compare carry-chain bit 4	full_add	Mode 2: OAM Scan
GOSO	Scan counter bit 2	dffr	Mode 2: OAM Scan
GOVU	LCDC.2 mask	or2	LCDC Structure	Mode 2: OAM Scan
GUFY	Volume saturation detector aggregate	or2	Sweep and Envelope
GUGU	Channel-disable latch (q_n = `ch3_fdis`)	nand_latch	CH3: Wave Channel
GUNE	SCY bit-6 read driver	not_if0	Register Reads
GUNY	CH4 `gary` reset (NOR `apu_reset`, `ch4_restart`)	nor2	CH4: Noise Channel
GUSU			Mode 2: OAM Scan
GUVA	= NOT(YDUG) — slot-0 match select	nor2	Mode 3: The Sprite Pipeline
GUVU	NOT(FUWA) — Y-compare sum bit 5, complemented	not_x1	Mode 2: OAM Scan
GYBA	CH4 divider-enable-latch clock (`= NOT ch4_1mhz`)	not_x1	CH4: Noise Channel
GYDA	NOT(GOJU) — Y-compare sum bit 6, complemented	not_x1	Mode 2: OAM Scan
GYKY	Carry-chain bit 3	full_add	Mode 2: OAM Scan
GYRA	Trigger-pulse retime DFF (GYTA on `ch3_2mhz`; feeds FAJU)	dffr	CH3: Wave Channel
GYSU	`ch4_start` capture DFF (clk `apu_phi`)	dffr	CH4: Noise Channel
GYTA	CH3 trigger self-clear delay	dffr	CH3: Wave Channel
GYZA	SCY bit-7 read driver	not_if0	Register Reads
GYZO	SCY bit-5 read driver	not_if0	Register Reads
HAFE	JOPA reset driver (pace 0)	nor4	Sweep and Envelope
HAMA	`hama_512khz` buffer (`= NOT jeso_n`)	not_x4	CH4: Noise Channel
HAPE	CH4 LFSR state bit	dffr	CH4: Noise Channel
HAZO	CH4 trigger nor_latch (feeds `ch4_restart.d`)	nor_latch	CH4: Noise Channel
HEFO	CH3 divider toggle clock (NOR stage)	nor2	CH3: Wave Channel
HENO	CH4 LFSR state bit	dffr	CH4: Noise Channel
HEPA	CH4 LFSR state bit	dffr	CH4: Noise Channel
HEPO	Saturation capture	dffr	Sweep and Envelope
HEPU	CH2 divider bit 9	tffnl	CH1/CH2: Pulse Channels
HERA	CH3 divider load enable (active-low)	nor2	CH3: Wave Channel
HERO	CH2 divider bit 10 (MSB)	tffnl	CH1/CH2: Pulse Channels
HEVY	CH2 divider bit 8	tffnl	CH1/CH2: Pulse Channels
HEZU	CH4 LFSR output bit	dffr	CH4: Noise Channel
HOFO	Volume bit-0 toggle clock	or3	Sweep and Envelope
HOGA	NR44 trigger-bit (`d7`) write strobe → `ch4_start`	drlatch_ee	CH4: Noise Channel
HORU	`horu_512hz` buffer chain stage	not_x3	APU Clock Tree and Frame Sequencer
HORY	CH4 LFSR state bit	dffr	CH4: Noise Channel
HUCE	CH4 prescaler load enable (`= NOT gofu`)	not_x1	CH4: Noise Channel
HUNO	CH3 overflow capture (/2 toggle)	dffr	CH3: Wave Channel
HURA	CH4 LFSR feedback XNOR (the two XNOR taps)	xnor	CH4: Noise Channel
HYFE	CH1 divider bit 1	tffnl	CH1/CH2: Pulse Channels
HYFO	CH3 overflow detector (NOT stage)	not_x1	CH3: Wave Channel
HYKE	CH1 divider bit 5	tffnl	CH1/CH2: Pulse Channels
HYLY	Envelope counter load enable (NOR stage)	nor2	Sweep and Envelope
HYNO	CH4 prescaler terminal-count (`jyfu&jyre&jyco`)	and3	CH4: Noise Channel
HYRO	CH4 LFSR state bit	dffr	CH4: Noise Channel
JAJU	CH4 LFSR state bit	dffr	CH4: Noise Channel
JAKE	Envelope counter load enable (NOT stage)	not_x1	Sweep and Envelope
JAPU	CH3 divider bit 10 (MSB)	tffnl	CH3: Wave Channel
JAVO	CH4 LFSR state bit	dffr	CH4: Noise Channel
JEMA	CH1 divider bit 4	tffnl	CH1/CH2: Pulse Channels
JEME	Envelope-stop latch	nor_latch	Sweep and Envelope
JEPE	CH4 LFSR state bit (7-bit inject point)	dffr	CH4: Noise Channel
JERA	CH3 divider load-enable fan-out	not_x1	CH3: Wave Channel
JERY	`ch4_fdis` channel-disable latch	nand_latch	CH4: Noise Channel
JESO	CH4 free-running 512 kHz prescaler bit	dffr	CH4: Noise Channel
JEVY	Envelope counter bit 2	tffnl	Sweep and Envelope
JONA	Envelope counter bit 1	tffnl	Sweep and Envelope
JOPA	Envelope-fire latch	dffr	Sweep and Envelope
JORE	Envelope counter bit 0	tffnl	Sweep and Envelope
JOTO	CH4 LFSR feedback/chain-entry DFF	dffr	CH4: Noise Channel
JUPU	Envelope pace = 0 detector	nor3	Sweep and Envelope
JUTY	CH3 divider toggle clock (NOT stage)	not_x1	CH3: Wave Channel
JUXE	CH4 LFSR state bit	dffr	CH4: Noise Channel
JYCO	CH4 divisor prescaler bit 0 (loadable toggle)	tffnl	CH4: Noise Channel
JYFU	CH4 divisor prescaler bit 2 (loadable toggle)	tffnl	CH4: Noise Channel
JYJA	CH4 LFSR feedback-DFF clock (`= NOT ch4_lfsr_clk1`)	not_x1	CH4: Noise Channel
JYNA	Frame sequencer /2 → 64 Hz (envelope tap)	dffr	APU Clock Tree and Frame Sequencer	Post-Boot State
JYRE	CH4 divisor prescaler bit 1 (loadable toggle)	tffnl	CH4: Noise Channel
JYTY	CH1 divider bit 2	tffnl	CH1/CH2: Pulse Channels
KAFO	CH3 divider bit 6	tffnl	CH3: Wave Channel
KAHE	CPL source (AO22 LCDC.7 mux)	ao22	LCDC Structure	LCD Output
KANU	CH4 divisor-prescaler toggle clock (`= kyku`)	not_x1	CH4: Noise Channel
KASA	CPL PPU-clock source (LCD-on arm)	not	LCD Output
KASO	CH3 divider load enable (bits 4–7)	not_x1	CH3: Wave Channel
KAVU	CH4 LFSR 7-bit-mode feedback inject	ao22	CH4: Noise Channel
KEBO	FR PPU-clock source (LCD-on arm)	not	LCD Output
KEDY	Mux selector complement (LCDC.7=0 arm)	not	LCD Output
KEJU	CH3 divider bit 8	tffnl	CH3: Wave Channel
KEMU	CH3 divider bit 3	tffnl	CH3: Wave Channel
KENO	CH3 divider bit 7	tffnl	CH3: Wave Channel
KEPA	CH3 divider bit 5	tffnl	CH3: Wave Channel
KESE	CH3 divider ripple inverter (bits 8–10)	not_x1	CH3: Wave Channel
KETU	CH4 LFSR state bit	dffr	CH4: Noise Channel
KEZA	CH3 divider bit 9	tffnl	CH3: Wave Channel
KOFO	FR pad driver	not	LCD Output
KOMU	CH4 LFSR state bit	dffr	CH4: Noise Channel
KONY	CH4 prescaler-clock gate inverter stage	not_x1	CH4: Noise Channel
KUNU	CH3 divider bit 2	tffnl	CH3: Wave Channel
KUPA	FR source (AO22 LCDC.7 mux)	ao22	LCDC Structure	LCD Output
KUPE	CH3 divider bit 1	tffnl	CH3: Wave Channel
KUTA	CH4 LFSR state bit	dffr	CH4: Noise Channel
KUTU	CH3 divider bit 0	tffnl	CH3: Wave Channel
KUZY	CH4 LFSR state bit	dffr	CH4: Noise Channel
KYGU	CH3 divider bit 4	tffnl	CH3: Wave Channel
KYKO	CH3 divider load enable (bits 0–3)	not_x1	CH3: Wave Channel
KYKU	CH4 prescaler-clock gate (`ch4_fdis OR jeso_512k`)	or2	CH4: Noise Channel
KYMO	CPL pad driver	not	LCD Output
KYNA	CH1 divider bit 3	tffnl	CH1/CH2: Pulse Channels
KYPE	CH1 divider ripple inverter (bits 4–7)	not_x1	CH1/CH2: Pulse Channels
KYRU	CH3 divider ripple inverter (bits 4–7)	not_x1	CH3: Wave Channel
KYVO	Envelope counter-at-max detector	and3	Sweep and Envelope
KYWY	CH4 LFSR state bit	dffr	CH4: Noise Channel
LACE	BGP bit-4 read driver	not_if0	Register Reads
LAFO	LY bit 7	dffr	Line Counters	Register Reads
LAJU	OBP1 bit-0 read driver	not_if0	Register Reads
LALU	STAT interrupt latch (IF bit 1)	dffsr	STAT Interrupts	Interrupt Dispatch, The IF Register
LAMA	LY reset	nor2	Line Counters	Register Reads, Mode Transitions, CPU-Visible Mode Boundaries
LAPE			Mode 3: The Sprite Pipeline
LARA			OAM DMA
LARY	BGP bit-7 read driver	not_if0	Register Reads
LAVY			OAM DMA
LAXU	Fetch counter bit 0	dffr	The Clock Tree	Mode 3: The BG Pipeline, Scanline and Frame Timing, Races
LEBA	OBP1 bit-6 read driver	not_if0	Register Reads
LEBO	Fetch-counter gated clock	nand2	Mode 3: The BG Pipeline	Scanline and Frame Timing
LEFE			Mode 3: The Sprite Pipeline
LEGU			Mode 3: The BG Pipeline
LELU	OBP1 bit-7 read driver	not_if0	Register Reads
LEMA	LY bit 5	dffr	Line Counters
LEPA	OBP1 bit-1 read driver	not_if0	Register Reads
LESU			Mode 3: The Sprite Pipeline
LESY			Mode 3: The Sprite Pipeline
LEXA	LY bit 2	dffr	Line Counters
LOBE	BGP bit-3 read driver	not_if0	Register Reads
LOBY	POKY reset driver	not_x1	Rendering Mode Control	Mode 3: The BG Pipeline
LODE	OBP1 bit-2 read driver	not_if0	Register Reads
LODY	BGP bit-6 read driver	not_if0	Register Reads
LOGO	DMA bus-read window	not_x1	OAM DMA
LOKA	WY bit-3 read driver	not_if0	Register Reads
LOKY			OAM DMA
LOLE	WX bit-3 read driver	not_if0	Register Reads
LOMA			Mode 3: The BG Pipeline	Races
LONY	Tile-fetch latch	nand_latch	Rendering Mode Control	Scanline and Frame Timing
LOPE	IF[0] capture (VBlank)	dffsr	Scanline and Frame Timing	The IF Register
LOTA			Mode 3: The Sprite Pipeline
LOTE	= NOT(MUMY) — OBP1 read drivers' `ena_n`	not_x1	Register Reads
LOVA	WX bit-0 read driver	not_if0	Register Reads
LOVU	LY bit 4	dffr	Line Counters
LOZE			Mode 3: The BG Pipeline	Mode 3: The Sprite Pipeline
LUGA	OBP1 bit-5 read driver	not_if0	Register Reads
LUKY	OBP1 bit-4 read driver	not_if0	Register Reads
LUMA	`dma_addr_ext` driver	not_x1	OAM DMA
LUNA	Temp-latch enable chain	not / nand3	Mode 3: The BG Pipeline	Races
LURY			Rendering Mode Control
LUZO			Mode 3: The BG Pipeline
LYCO	LY bit-2 read driver	not_if0	Register Reads
LYDO	LY bit 3	dffr	Line Counters
LYFA			Register Writes
LYHA			Line Counters	Mode Transitions
LYKA	BGP bit-5 read driver	not_if0	Register Reads
LYKU			Mode 3: The Sprite Pipeline
LYME	Sprite palette pipe output stage (`sprite_px_palette`)	dffsr	Mode 3: The Sprite Pipeline
LYRY	"Fetch complete" combinational	not_x1	Mode 3: The BG Pipeline	Mode 3: The Sprite Pipeline
LYZA	OBP1 bit-3 read driver	not_if0	Register Reads
LYZU	Fetch counter bit 0 sample	dffr	The Clock Tree	Rendering Mode Control, Mode 3: The BG Pipeline, Scanline and Frame Timing
MACU			Mode 3: The BG Pipeline
MAKA			OAM DMA
MARA	WX bit-7 read driver	not_if0	Register Reads
MASO			Mode 3: The Sprite Pipeline
MATO	LY bit 6	dffr	Line Counters
MATU			OAM DMA
MECO	FR PPU-clock feeder	(DFF chain)	LCD Output
MEDA	LCD vertical-sync source	dffr	The Clock Tree	Line Counters, LCD Output, Mode Transitions
MEFU			Mode 3: The Sprite Pipeline
MEGA	WY bit-4 read driver	not_if0	Register Reads
MEGU			Mode 3: The BG Pipeline
MEHE	NUNU clock buffer	not	Window Control
MEKE	Reload enable chain	not / nand3	The Timer
MELE	WX bit-4 read driver	not_if0	Register Reads
MERA	WY bit-7 read driver	not_if0	Register Reads
MERY	Wrap detect	nor2	The Timer
MESU	Fetch counter bit 1	dffr	Mode 3: The BG Pipeline	Scanline and Frame Timing
METE			Mode 3: The BG Pipeline	Races
MEVE			Mode 3: The Sprite Pipeline
MEXU			The Timer
MOBA	Wrap capture	dffr	The Timer	HALT and EI, The IF Register
MOCE	Self-stop condition	nand3	The Clock Tree	Mode 3: The BG Pipeline, Mode 3: The Sprite Pipeline, Post-Boot State
MODA	Sprite attribute pipe stage	dffsr	Mode 3: The Sprite Pipeline
MODU			Mode 3: The BG Pipeline
MOFO			Mode 3: The Sprite Pipeline
MOJU			Mode 3: The BG Pipeline
MOKA	OBP1 palette AO2222 combiner	ao2222	LCD Output
MOKO	WX bit-2 read driver	not_if0	Register Reads
MOLU	DMA read enable (AND2 with `ppu_rd`)	and2	Register Reads
MORY	DMA-vs-CPU address MUX select source	nand2	OAM DMA
MOSU	Window trigger	not_x2	Mode 3: The BG Pipeline	Window Control, Mode Transitions
MOXE	ALET complement (fine-scroll path)	not_x1	The Clock Tree	Mode 3: The BG Pipeline, Races
MUDE	LX reset	nor2	Line Counters
MUFE	WX bit-5 read driver	not_if0	Register Reads
MUKA	WX bit-1 read driver	not_if0	Register Reads
MUKU			Mode 3: The BG Pipeline
MULY	WX bit-6 read driver	not_if0	Register Reads
MUMY	OBP1 read enable (AND2 with `ppu_rd`)	and2	Register Reads
MURE	`s_pad` (VSYNC) driver	not_x1	LCD Output
MUWY	LY bit 0	dffr	Line Counters	Register Reads, Mode 2: OAM Scan, Mode Transitions
MYDE			Mode 3: The BG Pipeline
MYJY			Mode 3: The BG Pipeline
MYRO	LY bit 1	dffr	Line Counters
MYTA	FRAME_END capture	dffr	The Clock Tree	Line Counters, Rendering Mode Control, Mode Transitions
MYTE			OAM DMA
MYTU			Mode 3: The Sprite Pipeline
MYVO	ALET complement	not_x1	The Clock Tree	Mode 3: The BG Pipeline, Scanline and Frame Timing, Races
MYZO			Mode 3: The Sprite Pipeline
NAFY			Mode 3: The BG Pipeline	Races, Post-Boot State
NAPO			The Clock Tree
NASA			Mode 3: The BG Pipeline
NATY			Mode 3: The Sprite Pipeline
NAXY			OAM DMA
NAZE			Window Control
NEDA			Mode 3: The BG Pipeline
NEFO			Mode 3: The BG Pipeline
NELE	WY decode completion	not / nand5 / not	Window Control
NEPO			Mode 3: The BG Pipeline
NERU	LY=0 decode	nor8	Line Counters	Mode Transitions
NETA	VURY enable producer (tile-data stages)	and2	Mode 3: The BG Pipeline
NEVU			Window Control
NOCU	`in_window` driver	not	Mode 3: The BG Pipeline
NOFU			Mode 3: The BG Pipeline	Races
NOGY	WX register match decoder	nand5	Window Control
NOJO			Window Control
NOKO	FRAME_END decode	and4	Line Counters	Rendering Mode Control, Mode Transitions
NOLO			OAM DMA
NOPA	Window mode	dffr	The Clock Tree	Window Control, Scanline and Frame Timing, Races
NOZO			Mode 3: The BG Pipeline
NUDU			Mode 3: The BG Pipeline
NUFA			Window Control
NUGA			The Timer
NUKE	Sprite attribute pipe stage	dffsr	Mode 3: The Sprite Pipeline
NUKO	WX match	not	Mode 3: The BG Pipeline	Window Control
NULY	Sprite-visibility mask	nor2	Mode 3: The Sprite Pipeline
NUNU	WX-match capture 2	dffr	Window Control
NUNY	Window-trigger pulse	and2	Window Control
NUPA			Window Control
NURA	BGP palette AO2222 combiner	ao2222	LCD Output
NURO			Mode 3: The Sprite Pipeline
NUVY	DMA bit-7 read driver	not_if1	Register Reads
NYBO	IF[2] capture	dffsr	The Timer	The IF Register
NYDU	NUGA pre-wrap capture	dffr	The Timer
NYDY			Mode 3: The BG Pipeline	Races
NYFO	Trigger buffer	not / not	Window Control
NYGO	= NOT(MOLU) — DMA read-enable inverter stage 1	not_x1	Register Reads
NYKA	Fetch-complete capture	dffr	The Clock Tree	Mode 3: The BG Pipeline, Window Control, Scanline and Frame Timing
NYLU			Mode 3: The Sprite Pipeline
NYPE			The Clock Tree	Line Counters, Rendering Mode Control, LCD Output
NYVA	Fetch counter bit 2	dffr	Mode 3: The BG Pipeline	Scanline and Frame Timing, Races
NYXU	BG fetch counter reset	nor3	Rendering Mode Control	Mode 3: The BG Pipeline, Mode 3: The Sprite Pipeline, Window Control
NYZE	Match capture (even)	dffr	The Clock Tree	Rendering Mode Control, Mode 3: The BG Pipeline, Scanline and Frame Timing
PABA	BGP bit-1 read driver	not_if0	Register Reads
PAFU	WY register match decoder	nand5	Window Control
PAGA			Window Control
PAGO			STAT Interrupts
PAHA	ROXY set driver	not_x1	Rendering Mode Control	Mode 3: The BG Pipeline
PAHO	PX-bit-3 capture	dffr	Rendering Mode Control	LCD Output, Scanline and Frame Timing, Post-Boot State
PALO	WY bits 4–7 + LCDC.5 decode	nand5	Window Control
PALU	Sprite attribute pipe stage	dffsr	Mode 3: The Sprite Pipeline
PALY	LY==LYC comparator	not_x1	STAT Interrupts	CPU-Visible Mode Boundaries, HALT and EI
PANE	DMA bit-3 read driver	not_if1	Register Reads
PANY	RYFA data driver (window/fine-scroll NOR)	nor2	Mode 3: The BG Pipeline	Mode 3: The Sprite Pipeline, Window Control
PARE	DMA bit-4 read driver	not_if1	Register Reads
PARU	Mode 1 condition	not_x1	STAT Interrupts
PASO	Fine-counter reset	nor2	Mode 3: The BG Pipeline	Post-Boot State
PATY	Pixel-mux output	or3	Mode 3: The Sprite Pipeline	LCD Output
PEBA			Mode 3: The Sprite Pipeline
PEBO			Window Control
PECU	Fine-counter gated clock	nand2	Mode 3: The BG Pipeline
PEDA			The Timer
PEFO			Mode 3: The Sprite Pipeline
PEFU			Mode 3: The Sprite Pipeline
PELA	WY bit-5 read driver	not_if0	Register Reads
PERO	Palette-output multiplexer signal	combinational	Palette Latches	LCD Output
PERU			The Timer
PEZO			Window Control
PODA	WY bit-1 read driver	not_if0	Register Reads
POFO	STAT bit-4 read driver (mode-1 enable, from `rufo_n`)	not_if0	Register Reads
POFY	Loop inverter + feedback	not_x1	LCD Output	Mode Transitions, Post-Boot State
POGU	`cpg_pad` (clock pulse gate) driver	not_x1	LCD Output
POHU	Match comparator	not_x1	Mode 3: The BG Pipeline
POKA	BG-pixel combine	nor3	LCD Output	Mode 3: The Sprite Pipeline
POKY	Pixel-pipe data ready	nor_latch	Rendering Mode Control	Mode 3: The BG Pipeline, Window Control, Scanline and Frame Timing
POLO	WY bit-6 read driver	not_if0	Register Reads
POLY	DMA bit-0 read driver	not_if1	Register Reads
POME	Loop AVAP gate	nor2	LCD Output	Mode Transitions
POMO			Window Control
POPU	VBlank capture	dffr	The Clock Tree	Line Counters, Rendering Mode Control, Mode Transitions
PORE			Mode 3: The BG Pipeline
PORY	NYKA pipeline stage	dffr	The Clock Tree	Mode 3: The BG Pipeline, Window Control, Scanline and Frame Timing
POTE	STAT bit-6 read driver (LYC enable, from `rugu_n`)	not_if0	Register Reads
POVA	Match pulse	and2	Rendering Mode Control	Register Reads, Mode 3: The BG Pipeline, LCD Output
POVY			The Timer
POWU			OAM and VRAM Access	OAM DMA
PUDU			Mode 3: The Sprite Pipeline
PUFY	LYC bit-7 read driver	not_if0	Register Reads
PUKU	Window hit-and-latch	nor2 / nor3	Window Control
PUKY	WX-match decode	nand5 / not / nand5 / not	Window Control
PUNU	WY bit-0 read driver	not_if0	Register Reads
PUPU			Register Writes
PUSY	= NOT(NYGO) — DMA read drivers' active-high `ena`	not_x1	Register Reads
PUXA	Match capture (odd)	dffr	The Clock Tree	Rendering Mode Control, Mode 3: The BG Pipeline, Scanline and Frame Timing
PUZO	STAT bit-3 read driver (mode-0 enable, from `roxe_n`)	not_if0	Register Reads
PYBO			Mode 3: The BG Pipeline	LCD Output
PYCO	WX-match capture 1	dffr	Window Control
PYGO	PORY pipeline stage	dffr	The Clock Tree	Rendering Mode Control, Mode 3: The BG Pipeline, Scanline and Frame Timing
PYGU	WY bit-2 read driver	not_if0	Register Reads
PYJO			Mode 3: The Sprite Pipeline
PYJU	Tile-index bit-7 capture DFF	dffr_cc_q	Mode 3: The BG Pipeline
PYNU	Window-armed latch	nor_latch	Register Reads	Mode 3: The BG Pipeline, Window Control
RACE	LYC bit-4 read driver	not_if0	Register Reads
RACO			OAM and VRAM Access
RAGE			The Timer
RAHU			OAM and VRAM Access
RAJY	BG plane A output (LCDC.0 gated)	and2	LCDC Structure	Mode 3: The Sprite Pipeline, LCD Output
RALU			Mode 3: The BG Pipeline
RALY	DMA bit-5 read driver	not_if1	Register Reads
RAMA			Mode 3: The Sprite Pipeline
RAMU			Mode 3: The Sprite Pipeline
RAPE			STAT Interrupts
RARO	BGP bit-0 read driver	not_if0	Register Reads
RATE			The Timer
RAVO	LD1 / LD0 drivers	not	Register Reads	LCD Output
RAZU	LYC bit-2 read driver	not_if0	Register Reads
REDO	BGP bit-2 read driver	not_if0	Register Reads
REDY	LYC bit-3 read driver	not_if0	Register Reads
REFE			STAT Interrupts
REGA	TIMA bits 0–7	tffnl (toggle FF with load)	The Timer
REJO	WY-match frame latch	nor_latch	Mode 3: The BG Pipeline	Window Control, Scanline and Frame Timing
REMA	DMA bit-2 read driver	not_if1	Register Reads
REMY	LD0 pad driver	not_x2	Register Reads	LCD Output
RENE	Drain-detect stage 2	dffr	The Clock Tree	Rendering Mode Control, Mode 3: The BG Pipeline, Mode 3: The Sprite Pipeline
REPU	REJO reset	or2	Window Control	Scanline and Frame Timing
RESU	DMA bit-6 read driver	not_if1	Register Reads
RETU	LYC bit-0 read driver	not_if0	Register Reads
REVO			OAM and VRAM Access
REWO			Mode 3: The Sprite Pipeline
ROBY			Mode 3: The Sprite Pipeline
ROCO			Window Control
ROCY	Per-bit data-pad tri-state enable chain	combinational	OAM and VRAM Access
ROFO	DMA bit-1 read driver	not_if1	Register Reads
ROGA	Fine count bit 1	dffr	Mode 3: The BG Pipeline
ROGE	WY match	not	Window Control
ROKA			Mode 3: The Sprite Pipeline
ROMO	SUVU NAND4 input (POKY inverter)	not_x1	Mode 3: The BG Pipeline
RONE	Drain-gated match aggregate	nand4	Mode 3: The BG Pipeline
ROPE	= NAND2(SOHA, RYCU) — $FExx decode stage	nand2	OAM and VRAM Access
ROPO	LY==LYC synced match	dff17	The Clock Tree	Line Counters, Register Reads, STAT Interrupts
ROPY	Mode 3 inverter for VRAM enables	not_x1	Rendering Mode Control	OAM and VRAM Access
RORU			OAM DMA
ROSA	Sprite attribute pipe stage	dffsr	Mode 3: The Sprite Pipeline
ROSY			Mode 3: The Sprite Pipeline
ROXE	STAT.3/.4/.5/.6 enables	drlatch_ee	STAT Interrupts
ROXO	Inverted CLKPIPE buffer (fine-scroll clock source)	not_x1	Mode 3: The BG Pipeline	LCD Output
ROXY	Fine-scroll gate	nor_latch	Rendering Mode Control	Mode 3: The BG Pipeline, Scanline and Frame Timing, Post-Boot State
ROZE	Fine-counter self-stop	nand3	Mode 3: The BG Pipeline
RUBU	Fine count bit 2	dffr	Mode 3: The BG Pipeline
RUBY			The Timer
RUDA			Mode 3: The Sprite Pipeline
RUFO			STAT Interrupts
RUGO	Sprite attribute pipe stage	dffsr	Mode 3: The Sprite Pipeline
RUGU			STAT Interrupts
RUJU	Loop OR combiner	or3	LCD Output
RUPO	STAT bit 2 visible latch	nor_latch	STAT Interrupts
RUTA	BG plane B gated by sprite priority	and2	LCD Output
RUTU	LINE_END capture	dffr	The Clock Tree	Line Counters, Rendering Mode Control, Register Writes
RUZE	ST pad buffer	not_x3	LCD Output
RYCE	One-shot fire	and2	Mode 3: The BG Pipeline	Mode 3: The Sprite Pipeline
RYCU	ROPE input (= NOT(`fexx_ffxx_n`))	not_x1	OAM and VRAM Access
RYDU			Mode 3: The Sprite Pipeline
RYDY	Window hit	nor3	Mode 3: The BG Pipeline	Mode 3: The Sprite Pipeline, Window Control
RYFA	Drain-detect stage 1	dffr	Rendering Mode Control	Mode 3: The BG Pipeline, Mode 3: The Sprite Pipeline, Window Control
RYFU	BG plane A gated by sprite priority	and2	Mode 3: The Sprite Pipeline	LCD Output
RYKU	Fine count bit 0	dffr	The Clock Tree	Mode 3: The BG Pipeline
RYNO			LCD Output
RYPO	CP pad driver	not_x3	LCD Output
RYSA			Mode 3: The BG Pipeline
RYVE			Register Writes
SABE	Gated fetch clock	nand2	Mode 3: The Sprite Pipeline	Scanline and Frame Timing
SACU	Pixel pipe shift clock (CLKPIPE)	or2	Register Writes	Register Reads, Mode 2: OAM Scan, Mode 3: The BG Pipeline
SADU			Rendering Mode Control	Register Reads, CPU-Visible Mode Boundaries
SADY			Mode 3: The BG Pipeline
SAJA			Mode 3: The Sprite Pipeline
SANU	LINE_END decode	and4	The Clock Tree	Line Counters, Rendering Mode Control, Mode Transitions
SARY	WY-match sampler	dffr	Window Control
SASY	STAT bit-5 read driver (mode-2 enable, from `refe_n`)	not_if0	Register Reads
SATA	Sprite attribute pipe stage	dffsr	Mode 3: The Sprite Pipeline
SAVY	PX bit 1	dffr	Mode 3: The BG Pipeline
SAXO	LX bit 0	dffr	The Clock Tree	Line Counters, Races, Post-Boot State
SAZO			OAM and VRAM Access
SEBA	Fetch-counter TULY capture stage 3	dffr	Rendering Mode Control	Mode 3: The Sprite Pipeline, Scanline and Frame Timing, Races
SEBY	VRAM read-latch enable	not_x1	OAM and VRAM Access
SECA	TAKA set net	nor3	Mode 3: The Sprite Pipeline	Mode Transitions
SEGA			Mode 3: The Sprite Pipeline
SEGO	STAT bit-2 read driver (LYC match, from `rupo_n`)	not_if1	Register Reads
SEGU	Buffered CLKPIPE	not_x4	Mode 3: The BG Pipeline	Mode 3: The Sprite Pipeline, Scanline and Frame Timing, Post-Boot State
SEKO	Tile-boundary drain detector	nor2	Mode 3: The BG Pipeline	Mode 3: The Sprite Pipeline, Window Control
SELA			Mode Transitions	STAT Interrupts
SELE			Mode 3: The Sprite Pipeline
SEMO			Mode 3: The Sprite Pipeline
SEMU	CP pixel-clock source (pre-buffer)	or2	LCD Output
SEPA	STAT write enable	and2	Register Writes
SERE	CPU data-bus enable stage 2	and2	OAM and VRAM Access
SETU			Mode 3: The BG Pipeline
SOBO			Mode 3: The BG Pipeline
SOBU	Fetch request	dffr	Mode 3: The BG Pipeline	Mode 3: The Sprite Pipeline, Scanline and Frame Timing
SOCY	Window-halt gate	not_x1	Mode 3: The BG Pipeline	Window Control, Post-Boot State
SOGU	TIMA clock gate	nor2	The Timer
SOHA	ROPE input (= NOT(`ffxx`))	not_x1	OAM and VRAM Access
SOHU			Mode 3: The BG Pipeline	LCD Output
SOHY	Write-strobe driver	nand2	OAM and VRAM Access
SOKA			Mode 3: The Sprite Pipeline
SOMY	Sprite attribute pipe stage	dffsr	Mode 3: The Sprite Pipeline
SONO	1 MHz LINE_END capture clock (TALU complement)	not_x1	The Clock Tree	Line Counters, Rendering Mode Control, Register Writes
SOVU			STAT Interrupts
SOWO	TEKY re-trigger block (TAKA inversion)	not_x1	Mode 3: The Sprite Pipeline
SOZU	Fine-count bit 2 match	xnor	Mode 3: The BG Pipeline
STOP			OAM DMA	The Timer
SUBO			STAT Interrupts
SUDA	Trigger one-shot partner	dffr	Mode 3: The BG Pipeline	Mode 3: The Sprite Pipeline, Scanline and Frame Timing
SUDE	LX bit 4	dffr	Line Counters
SUHA	Per-bit SCX match	xnor	Mode 3: The BG Pipeline
SUKO	Condition combining gate	ao2222	STAT Interrupts	The IF Register
SUNY			Mode 3: The Sprite Pipeline
SUTO			Mode 3: The Sprite Pipeline
SUVU	Startup-/window-restart NAND4 (TAVE input)	nand4	Rendering Mode Control	Mode 3: The BG Pipeline
SUZU	Window-activation trigger	not	Mode 3: The BG Pipeline	Window Control
SYBE			Mode 3: The BG Pipeline
SYBY	Fine-count bit 1 match	xnor	Mode 3: The BG Pipeline
SYGU			The Clock Tree	LCD Output, Races
SYLO	RYDY first inverter (consumer-chain stage 1)	not	Mode 3: The BG Pipeline	Window Control
SYSY			OAM and VRAM Access
TACA			Mode 3: The BG Pipeline
TACE	Global DAC-off term — `amp_en_n` = AND4 of the four `ch*_amp_en_n`	and4	CH3: Wave Channel
TADE	BG plane B output (LCDC.0 gated)	and2	LCDC Structure	LCD Output
TADY	VOGA + PX-counter reset	nor2	Rendering Mode Control	Mode 3: The BG Pipeline, Window Control, Mode Transitions
TAHA	LX bit 5	dffr	Line Counters
TAKA	Fetch-running latch	nand_latch	Mode 3: The BG Pipeline	Mode 3: The Sprite Pipeline, Window Control, Mode Transitions
TAKO			Mode 3: The BG Pipeline
TALU	1 MHz LX counter clock	not_x4	The Clock Tree	Line Counters, Register Writes, Register Reads
TAME	Self-stop	nand2	Mode 3: The Sprite Pipeline
TAPA	Mode 2 condition	and2	STAT Interrupts
TAPE			The Timer
TAPU	CUPA driver stage 2	not	Register Writes
TARU	Mode 0 condition	and2	STAT Interrupts
TAVA	SOBU clock gate	not_x1	Mode 3: The Sprite Pipeline
TAVE	Startup / window-restart trigger	not	Mode 3: The BG Pipeline	Mode 3: The Sprite Pipeline
TAXY	CPU-bus-phase strobe assembly	combinational	OAM and VRAM Access
TEBY	STAT bit-0 read driver (from SADU)	not_if1	Register Reads
TECY			The Timer
TEGO	= NOT(VAMA) — $FF49 active-high select	not_x2	Register Reads
TEKO			The Timer
TEKY	X-match trigger	and4	Mode 2: OAM Scan	Mode 3: The BG Pipeline, Mode 3: The Sprite Pipeline, Scanline and Frame Timing
TELU	LX bit 3	dffr	Line Counters
TEPA	NOT(mode3)	not_x1	Rendering Mode Control
TEPO	BGP write enable sub-signal	combinational	Register Writes	Palette Latches
TEPY	= NOT(VUSO) — BGP read drivers' `ena_n`	not_x1	Register Reads
TESE	Sprite fetch counter bit 2 (SFETCH_S2)	dffr	Mode 3: The Sprite Pipeline
TEVO	Tile-boundary / restart trigger	or3	Mode 3: The BG Pipeline	Mode 3: The Sprite Pipeline, Window Control, Mode Transitions
TOBA			Mode 3: The BG Pipeline	LCD Output
TOBE	FF41 read enable	and2	Register Reads
TOBU	TULY capture chain	dffr	Rendering Mode Control	Mode 3: The Sprite Pipeline, Scanline and Frame Timing, Races
TOCA	Upper-nibble clock	not	Mode 3: The BG Pipeline	Races
TOFU	Video reset	not	Rendering Mode Control	Mode 3: The BG Pipeline, LCD Output, Mode Transitions
TOLE	CPU data-bus enable stage 1	combinational	OAM and VRAM Access
TOLU	mode1 inverter	not_x1	STAT Interrupts	The IF Register
TOMU	RYDY second inverter (consumer-chain stage 2)	not	Mode 3: The BG Pipeline	Window Control
TOMY			Mode 3: The BG Pipeline
TORY			Mode 3: The Sprite Pipeline
TOXE	Fetch counter bits 0–2	dffr	The Clock Tree	Mode 3: The Sprite Pipeline
TOZA			OAM DMA
TUHU	PX bits 4–7	dffr	Mode 3: The BG Pipeline
TUKU	Sprite-trigger window block (consumer-chain stage 3)	not	Mode 3: The Sprite Pipeline	Window Control
TUKY			Mode 3: The BG Pipeline
TULY	Sprite fetch counter bit 1 (SFETCH_S1)	dffr	Mode 3: The Sprite Pipeline
TUTO			OAM and VRAM Access
TUVA	Inverter pair	not	STAT Interrupts	The IF Register
TUVO			OAM DMA	Mode 3: The Sprite Pipeline
TUXY	Window-trigger NAND (SUZU input)	nand2	Mode 3: The BG Pipeline	Window Control
TYCO			Mode 3: The Sprite Pipeline
TYFA	CLKPIPE gate	and3	Mode 3: The BG Pipeline	Scanline and Frame Timing, Post-Boot State
TYFO	Done decode B	dffr	Mode 3: The Sprite Pipeline	Scanline and Frame Timing
TYHO			OAM DMA
TYJY			OAM and VRAM Access
TYNO	Done decode A	nand3	Mode 3: The Sprite Pipeline
TYPO	LX bit 1	dffr	Line Counters
TYRY	LX bit 6	dffr	Line Counters	Post-Boot State
TYTA			Mode 3: The Sprite Pipeline
UBAL	CUPA driver stage 3	muxi	Register Writes
UBUL	IF[3] capture (Serial)	dffsr	The IF Register
UCOB			The Timer
UKAP	TAC mux chain	muxi	The Timer
UKUP	`reg_div16` bits 0–15	dff	The Timer
ULAK	IF[4] capture (Joypad)	dffsr	The IF Register
UMOB	CPL audio-clock source (LCD-off arm)	(external)	LCD Output
UPOF			The Timer
USEC	FR audio-clock source (LCD-off arm)	(external)	LCD Output
UVYT			OAM DMA
VAFE	LYC bit-6 read driver	not_if0	Register Reads
VAFO			Mode 3: The Sprite Pipeline
VAHA	LCDC bit-6 read driver	not_if0	Register Reads
VAMA	$FF49 address decode	nand5	Register Reads
VANU			Mode 3: The Sprite Pipeline
VARE			Mode 3: The Sprite Pipeline
VARO	= NOT(WAFU) — LY read drivers' `ena_n`	not_x1	Register Reads
VARY	= NOT(WOFA) — $FF41 active-high select	not_x2	Register Reads	Register Writes
VATO	LCDC bit-5 read driver	not_if0	Register Reads
VAVA	Priority mask pipe MSB / LSB	dffsr	Mode 3: The Sprite Pipeline	LCD Output
VAVE	NOT(TOBE) — STAT enable-bit read gate	not_x1	Register Reads
VAZU	LYC bit-5 read driver	not_if0	Register Reads
VCLK			LCD Output
VEGA	LY bit-0 read driver	not_if0	Register Reads
VEKU			Mode 3: The Sprite Pipeline
VELY	BGP write enable	and2	Register Writes	Register Reads
VENA	1 MHz toggle divider	dffr	The Clock Tree	Line Counters, Register Writes, Scanline and Frame Timing
VEVY	LCDC.6 → ~ma10 tri-state driver	not_if0	Mode 3: The BG Pipeline
VEZO	Mask pipe (LSB end)	dffsr	Mode 3: The Sprite Pipeline
VOCA	= NOT(WORU) — $FF40 active-high select	not_x2	Register Reads	Register Writes
VOGA	H-Blank capture DFF	dffr	The Clock Tree	Rendering Mode Control, Mode 3: The BG Pipeline, Mode Transitions
VOJO	LYC bit-1 read driver	not_if0	Register Reads
VOKE	LCDC bit-4 read driver	not_if0	Register Reads
VOMY	= NOT(WAXU) — WY read drivers' `ena_n`	not_x1	Register Reads
VONU	Fetch-counter TULY capture stage 2	dffr	Rendering Mode Control	Mode 3: The Sprite Pipeline, Scanline and Frame Timing, Races
VOSA	Sprite attribute pipe stage	dffsr	Mode 3: The Sprite Pipeline
VOTO			Mode 3: The Sprite Pipeline
VOTY			STAT Interrupts	The IF Register
VUJO			Window Control
VUMO	Sprite attribute pipe stage	dffsr	Mode 3: The Sprite Pipeline
VUMY	= NOT(WAGE) — $FF4B active-high select	not_x2	Register Reads
VUPY			Mode 3: The Sprite Pipeline
VURY	VUZA → ~ma12 tri-state driver	not_if1	Mode 3: The BG Pipeline
VUSA	Fetch-done aggregate	or2	Mode 3: The Sprite Pipeline
VUSO	BGP read enable (AND2 with `ppu_rd`)	and2	Register Reads
VUZA	TILE_SEL XOR tile-index MSB	nor2	Mode 3: The BG Pipeline
VYBO	Operational per-dot gate	nor3	Mode 3: The BG Pipeline	Mode 3: The Sprite Pipeline, Scanline and Frame Timing, Post-Boot State
VYCU	= NOT(WYZE) — WX read drivers' `ena_n`	not_x1	Register Reads
VYGA	= NOT(WYVO) — $FF4A active-high select	not_x2	Register Reads
VYNE	LY bit-4 read driver	not_if0	Register Reads
VYNO	Window line counter LSB	dffr	Window Control
VYPU	int_vbl driver	not_x3	The IF Register
VYRE	LCDC read enable (AND2 with `ppu_rd`)	and2	Register Reads
VYSA			Mode 3: The Sprite Pipeline
VYXE			LCDC Structure	LCD Output
VYZO	LX bit 2	dffr	Line Counters
WAFU	LY read enable (AND2 with `ppu_rd`)	and2	Register Reads
WAGE	$FF4B address decode	nand5	Register Reads
WAGO	8×16 half-select	xor	Mode 3: The Sprite Pipeline
WAHE	OAM wordline-driver precharge (`oam_wldrv_precharge_n` = NOT(WUJY))	not_x3	OAM and VRAM Access
WAMA	LY bit-5 read driver	not_if0	Register Reads
WAME	OAM output-enable inverter	not_x2	OAM and VRAM Access
WARE	SCY bit-0 read driver	not_if0	Register Reads
WARU	LCDC write enable	and2	Register Writes	Mode 3: The BG Pipeline
WATE	$FF46 address decode	nand5	Register Reads
WAVO	LY bit-6 read driver	not_if0	Register Reads
WAVU	$FF43 address decode	nand5	Register Reads
WAXU	WY read enable (AND2 with `ppu_rd`)	and2	Register Reads
WAZO	WUJY input — wordline-precharge timing	or3	OAM and VRAM Access
WAZY	Window line counter clock	not_x1	Window Control
WEBA			Mode 3: The Sprite Pipeline
WEBU	$FF42 address decode	nand5	Register Reads
WEFY			Mode 3: The Sprite Pipeline
WEGO	XYMU set driver	or2	Rendering Mode Control	Mode 3: The BG Pipeline, Mode Transitions
WEKU	= NOT(XYLY) — LYC read drivers' `ena_n`	not_x1	Register Reads
WELO	Slot-0 X store bit 4 (holds NOT(X))	drlatch_ee	Mode 3: The Sprite Pipeline
WERA	= NOT(WYBO) — $FF47 active-high select	not_x2	Register Reads	Register Writes
WETA	$FF48 address decode	nand5	Register Reads
WETY	$FF45 address decode	nand5	Register Reads
WEWY	Scan counter bit 1	dffr	Mode 2: OAM Scan
WEXU	LCDC.4 (TILE_SEL) latch	drlatch_ee	LCDC Structure	Mode 3: The BG Pipeline
WEZE	LY bit-7 read driver	not_if0	Register Reads
WODA	Sprite attribute pipe stage	dffsr	Mode 3: The Sprite Pipeline
WODU	Mode 0 condition	and2	Rendering Mode Control	Register Writes, Register Reads, Mode 3: The BG Pipeline
WOFA	$FF41 address decode	nand5	Register Reads
WOJO	LCD control phase	nor2	The Clock Tree
WOJU	Slot-0 X comparator bit 4 (XOR vs NOT(PX))	xor	Mode 3: The Sprite Pipeline
WOJY	LY bit-3 read driver	not_if0	Register Reads
WOKY	LCDC.6 (WIN_MAP) latch	drlatch_ee	LCDC Structure	Mode 3: The BG Pipeline
WONE			OAM DMA	Mode 2: OAM Scan
WONY	SCX bit-3 read driver	not_if0	Register Reads
WOPE			Mode 3: The Sprite Pipeline
WORA			Mode 3: The Sprite Pipeline
WORU	$FF40 address decode	nand5	Register Reads
WOSU	WUVU sampler	dffr	The Clock Tree	Scanline and Frame Timing
WOTA	Y-compare decoder	nand6	Mode 2: OAM Scan
WOTE	Slot-0 X store bit 6 (holds NOT(X))	drlatch_ee	Mode 3: The Sprite Pipeline
WOVU	OAM bitline precharge driver (`oam_bl_precharge_n` = NOT(COTA))	not_x2	OAM and VRAM Access
WOXA	Plane-A pixel-output gate	and2	LCDC Structure	Mode 3: The Sprite Pipeline
WUDA			Mode 2: OAM Scan
WUFU	OBP0 palette AO2222 combiner	ao2222	LCD Output
WUFY			Mode 3: The Sprite Pipeline
WUGA	STAT bit-1 read driver (from XATY)	not_if1	Register Reads
WUHU	Y-compare carry-chain bit 7	full_add	Mode 2: OAM Scan
WUJY	= NAND2(WAZO, `oam_bl_precharge_n`) — wordline-precharge timing	nand2	OAM and VRAM Access
WUKA	LCDC bit-3 read driver	not_if0	Register Reads
WUKO	VEVY enable (window tilemap stage)	not_x2	Mode 3: The BG Pipeline
WUKY	Y-flip term	not_x1	Mode 3: The Sprite Pipeline
WURU	Sprite attribute pipe stage	dffsr	Mode 3: The Sprite Pipeline
WUTY	Fetch done	not	Mode 2: OAM Scan	Mode 3: The BG Pipeline, Mode 3: The Sprite Pipeline
WUVA	LY bit-1 read driver	not_if0	Register Reads
WUVU	2 MHz toggle divider	dffr	The Clock Tree	Register Writes, Mode 2: OAM Scan, Scanline and Frame Timing
WYBO	$FF47 address decode	nand5	Register Reads
WYCE	= NOT(VYRE) — LCDC read drivers' `ena_n`	not_x1	Register Reads
WYFU	Sprite attribute pipe stage	dffsr	Mode 3: The Sprite Pipeline
WYHO			Mode 3: The Sprite Pipeline
WYJA	OAM write enable (combined)	ao21	OAM and VRAM Access	OAM DMA, CPU-Visible Mode Boundaries
WYJU	LCDC bit-2 read driver	not_if0	Register Reads
WYLE	$FF44 address decode	nand5	Register Reads
WYMO			LCDC Structure
WYNO			OAM DMA	Mode 2: OAM Scan
WYPO	LCDC bit-0 read driver	not_if0	Register Reads
WYSO			Mode 3: The Sprite Pipeline
WYVO	$FF4A address decode	nand5	Register Reads
WYZA	Slot-0 X comparator bit 6 (XOR vs NOT(PX))	xor	Mode 3: The Sprite Pipeline
WYZE	WX read enable (AND2 with `ppu_rd`)	and2	Register Reads
XAFO	LCDC.3 (BG_MAP) latch	drlatch_ee	LCDC Structure	Mode 3: The BG Pipeline
XAFU			OAM DMA	Mode 2: OAM Scan
XAGE	Per-slot X match, FEFY group (active-low)	nand3	Mode 3: The Sprite Pipeline
XAJU	OBP0 bit-4 read driver	not_if0	Register Reads
XAKO	Slot-0 X store bit 7 (holds NOT(X))	drlatch_ee	Mode 3: The Sprite Pipeline
XANE	VRAM address tri-state-disable source	nor2	Rendering Mode Control	OAM and VRAM Access
XANO	"PX at terminal count" (inverted XUGU)	not_x1	Rendering Mode Control	Mode 3: The BG Pipeline, Mode Transitions, STAT Interrupts
XAPO			Rendering Mode Control	Mode 2: OAM Scan
XARO	= NOT(WEBU) — $FF42 active-high select	not_x2	Register Reads	Register Writes
XARY	OBP0 bit-0 read driver	not_if0	Register Reads
XATY			Rendering Mode Control	Register Reads, CPU-Visible Mode Boundaries
XAVY	= NOT(WAVU) — $FF43 active-high select	not_x2	Register Reads	Register Writes
XAWO	OBP0 bit-7 read driver	not_if0	Register Reads
XAXA	OBP0 bit-6 read driver	not_if0	Register Reads
XAYO	= NOT(WETA) — $FF48 active-high select	not_x2	Register Reads
XAYU	= NOT(WETY) — $FF45 active-high select	not_x2	Register Reads
XEBA	Slot-0 match, high-nibble collapse	nor4	Mode 3: The Sprite Pipeline
XEBU	LCDC bit-7 read driver	not_if0	Register Reads
XEDA	= NOT(WATE) — $FF46 active-high select	not_x2	Register Reads
XEDU	VRAM address tri-state enable	not_x2	OAM and VRAM Access
XEFY	Global sprite shifter parallel-load disable	not_x1	Mode 3: The Sprite Pipeline
XEGU			Mode 3: The Sprite Pipeline
XEHO	PX bit 0	dffr	Mode 3: The BG Pipeline
XENA	"No sprite match" (inverted FEPO)	not_x1	Rendering Mode Control	Mode 3: The BG Pipeline, Mode Transitions, STAT Interrupts
XEPE	Slot-0 X store bit 0 (holds NOT(X))	drlatch_ee	Mode 3: The Sprite Pipeline
XERO	LCDC bit-1 read driver	not_if0	Mode 3: The Sprite Pipeline	Register Reads
XETE	Sprite attribute pipe stage	dffsr	Mode 3: The Sprite Pipeline
XEZE			Mode 3: The BG Pipeline
XOBO	OBP0 bit-5 read driver	not_if0	Register Reads
XOCE			OAM DMA	Mode 2: OAM Scan
XODO	VID_RST signal	combinational	Register Writes	LCDC Structure, Scanline and Frame Timing
XODU	PX bit 2	dffr	Mode 3: The BG Pipeline
XOFO	PYNU reset (WIN_EN gate)	nand3	LCDC Structure	Window Control
XOGS			Interrupt Dispatch
XOGY	= NOT(WYLE) — $FF44 active-high select	not_x2	Register Reads
XOKE	OBP0 bit-1 read driver	not_if0	Register Reads
XONA	LCDC.7 storage latch	drlatch_ee	Register Writes	LCDC Structure
XOTA	WUVU clock	not_x1	The Clock Tree
XOTE			Mode 3: The Sprite Pipeline
XOVU			Mode 3: The Sprite Pipeline
XOZY	= NOT(XUFY) — OBP0 read drivers' `ena_n`	not_x1	Register Reads
XUBO			Register Writes
XUBY	OBP0 bit-3 read driver	not_if0	Register Reads
XUFY	OBP0 read enable (AND2 with `ppu_rd`)	and2	Register Reads
XUGU	Terminal count decode	nand5	Rendering Mode Control	Mode 3: The BG Pipeline, Window Control, Mode Transitions
XUJA			OAM DMA
XUJY	Sprite-fetch counter term in BYCU	combinational	OAM DMA	Mode 2: OAM Scan, OAM and VRAM Access
XUKE			Mode 3: The BG Pipeline
XULA	Plane-B pixel-output gate	and2	LCDC Structure	Mode 3: The Sprite Pipeline
XUNO	OBP0 bit-2 read driver	not_if0	Register Reads
XUNY	Slot-0 X store bit 5 (holds NOT(X))	drlatch_ee	Mode 3: The Sprite Pipeline
XUPY	2 MHz scan-counter clock (NOT(wuvu_n) = WUVU.q)	not_x2	The Clock Tree	Register Writes, Mode 2: OAM Scan, Mode 3: The BG Pipeline
XURE			Register Writes
XUSO	OAM Y-offset bit 0 latch (Mode 2) / tile-index bit 0 latch (Mode 3)	dlatch_ee	OAM DMA	Mode 2: OAM Scan, Mode 3: The Sprite Pipeline
XYDO	PX bit 3	dffr	Mode 3: The BG Pipeline	LCD Output, Races
XYFY	XOTA complement	not_x1	The Clock Tree
XYJU			Mode 3: The Sprite Pipeline
XYKY			OAM DMA	Mode 2: OAM Scan, Mode 3: The Sprite Pipeline
XYLE			Mode 3: The BG Pipeline
XYLO	LCDC.1 (OBJ_EN) register bit	drlatch_ee	LCDC Structure	Mode 2: OAM Scan, Mode 3: The Sprite Pipeline
XYLY	LYC read enable (AND2 with `ppu_rd`)	and2	Register Reads
XYMO	LCDC.2 (OBJ_SIZE) register bit	drlatch_ee	LCDC Structure	Mode 2: OAM Scan, Mode 3: The Sprite Pipeline
XYMU	Rendering-mode latch (active-low Mode 3 indicator)	nor_latch	Rendering Mode Control	Register Writes, OAM and VRAM Access, OAM DMA
XYSO			Mode 2: OAM Scan
XYVA	Parallel divider branch	not_x1	The Clock Tree
XYVO	VBlank decode	and2	Line Counters	Rendering Mode Control, Mode Transitions
YBEZ	Per-slot X match, FOVE group (active-low)	nand3	Mode 3: The Sprite Pipeline
YBOG			Mode 3: The Sprite Pipeline
YCEB			OAM DMA	Mode 2: OAM Scan
YDUG	Slot-0 X match (active-low)	nand3	Mode 3: The Sprite Pipeline
YDYV			OAM DMA	Mode 2: OAM Scan, Mode 3: The Sprite Pipeline
YFEL	Scan counter bit 0 (LSB)	dffr	Mode 2: OAM Scan
YFUN	Slot-0 X comparator bit 5 (XOR vs NOT(PX))	xor	Mode 3: The Sprite Pipeline
YGEM	Per-slot X match, FOVE group (active-low)	nand3	Mode 3: The Sprite Pipeline
YJEX			Mode 3: The Sprite Pipeline
YKUA			HALT and EI
YLAH	Slot-0 X store bit 1 (holds NOT(X))	drlatch_ee	Mode 3: The Sprite Pipeline
YLOR			OAM DMA	Mode 2: OAM Scan, Mode 3: The Sprite Pipeline
YLOZ	Per-slot X match, FEFY group (active-low)	nand3	Mode 3: The Sprite Pipeline
YLYC	OAM A-side / B-side write strobe drivers	per-byte selector	OAM and VRAM Access	OAM DMA
YNKW			HALT and EI
YNYC			OAM and VRAM Access	OAM DMA
YOII			Interrupt Dispatch	HALT and EI, The IF Register
YPUK	Slot-0 X comparator bit 7 (XOR vs NOT(PX))	xor	Mode 3: The Sprite Pipeline
YRUM			OAM DMA	Mode 2: OAM Scan
YSES			OAM DMA	Mode 2: OAM Scan
YSEX			OAM DMA	Mode 2: OAM Scan
YVEL			OAM DMA	Mode 2: OAM Scan
YZAB			Mode 3: The Sprite Pipeline
YZOS			Mode 3: The Sprite Pipeline
ZACW			Interrupt Dispatch
ZAGO			Mode 2: OAM Scan
ZAHA	Slot-0 X comparator bit 2 (XOR vs NOT(PX))	xor	Mode 3: The Sprite Pipeline
ZAIJ			Interrupt Dispatch	HALT and EI
ZAKO	Slot-0 match, low-nibble collapse	nor4	Mode 3: The Sprite Pipeline
ZAOC			Interrupt Dispatch
ZAXE			OAM DMA	Mode 2: OAM Scan
ZAXY	Buffer stage	not_x2	The Clock Tree
ZEBA	Slot-0 X comparator bit 1 (XOR vs NOT(PX))	xor	Mode 3: The Sprite Pipeline
ZECA			OAM DMA	Mode 2: OAM Scan, Mode 3: The Sprite Pipeline
ZEME	Buffer stage	not_x4	The Clock Tree
ZEZY			Mode 3: The Sprite Pipeline
ZFEX			Interrupt Dispatch
ZIVV			HALT and EI
ZJJE	`ime_pending` — "IME pending" SR latch (q drives dmg-sim wire `ime_state`)	sm83_srlatch_r_n	HALT and EI
ZKOG			Interrupt Dispatch
ZLOZ			Interrupt Dispatch
ZOGY	Slot-0 X comparator bit 0 (XOR vs NOT(PX))	xor	Mode 3: The Sprite Pipeline
ZOKY	Slot-0 X comparator bit 3 (XOR vs NOT(PX))	xor	Mode 3: The Sprite Pipeline
ZOLA	Slot-0 X store bit 2 (holds NOT(X))	drlatch_ee	Mode 3: The Sprite Pipeline
ZRSY	RETI / reset gating SR latch (q = `zrsy`)	sm83_srlatch_r_n	HALT and EI
ZUCA			OAM DMA	Mode 2: OAM Scan
ZULU	Slot-0 X store bit 3 (holds NOT(X))	drlatch_ee	Mode 3: The Sprite Pipeline
ZUVE			OAM DMA	Mode 2: OAM Scan
ZYTY			Mode 3: The Sprite Pipeline
ZYVE			Mode 3: The Sprite Pipeline
ZZOM			Interrupt Dispatch

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DMG Timing Specification

Appendix A: Signal Concordance