The Clock Tree

Every timing claim in this book ultimately reduces to "this cell captures on that edge of this clock". This chapter names the clocks. It follows the master clock from the crystal input through the buffer chain to the PPU's per-dot clock pair (ALET/MYVO), down the video divider chain to the per-M-cycle pair (TALU/SONO), and establishes the phase relationships the rest of the book leans on.

The master oscillator

The DMG-CPU B has a single crystal oscillator at 4.194304 MHz connected through the top-level input ck1_ck2 — the master clock from which all on-chip timing derives. Wherever this book says "the master clock" (including the propagation-delay origin used in Races), the referent is ck1_ck2.

One dot covers both edges of the master clock. ALET, the PPU's main 4 MHz clock, tracks the master clock in phase: ALET rising corresponds to ck1_ck2 rising after ~16.3 ge of buffer delay. MYVO = NOT(ALET) is the complementary clock — DFFs clocked by ALET capture on one edge, those clocked by MYVO on the other, both within a single dot. "One ALET half-cycle" and "one ATAL half-cycle" both mean half a dot.

Dot counts in this book are edge counts — independent of the simulation's delay model. Picosecond values come from the gate-level simulation's 244,000 ps dot period — see How to read the numbers.

Crystal to PPU clocks

The crystal feeds a NAND feedback pair (ANOS/AVET) that produces ATAL (the 4 MHz enable) and its complement ADEH. From ATAL the PPU clock tree branches through a buffer chain (AZOF → ZAXY → ZEME) to ALET (4 MHz PPU main clock) and its complements (MYVO, MOXE). A parallel branch (XYVA → XOTA) feeds the WUVU/VENA/WOSU video divider chain; VENA drives TALU (1 MHz LX-counter clock) and its complement SONO. The tree diagram shows the propagation hierarchy; the reference block catalogues each named cell.

ck1_ck2 (4.194 MHz crystal)
└── ANOS (nand2) / AVET (nand2) — feedback pair
    └── ATAL (not_x2) — 4 MHz buffered enable
        ├── ADEH = NOT(ATAL) — complement
        ├── [CPU phase generators: AFUR/ALEF/APUK/ADYK ring]
        └── AZOF (not_x6) = NOT(ATAL) — PPU clock buffer
            └── ZAXY (not_x2) = NOT(AZOF)
                └── ZEME (not_x4) = NOT(ZAXY)
                    ├── ALET (not_x2) = NOT(ZEME) — 4 MHz PPU main clock
                    │   ├── MYVO (not_x1) = NOT(ALET) — complementary to ALET
                    │   └── MOXE (not_x1) = NOT(ALET) — same phase as MYVO
                    └── XYVA (not_x1) = NOT(ZEME)
                        └── XOTA (not_x1) = NOT(XYVA)
                            ├── WUVU (dffr) — toggle, 2 MHz [clk=XOTA]
                            │   ├── VENA (dffr) — toggle, 1 MHz [clk=WUVU.~Q]
                            │   │   ├── TALU (not_x4) = NOT(vena_n) = VENA.q — LX counter clock, 1 MHz
                            │   │   │   └── SONO (not_x1) = NOT(TALU) = vena_n
                            │   │   └── [used as clock for per-dot DFFs]
                            │   └── WOSU (dffr) — samples WUVU on opposite edge [clk=XYFY]
                            └── XYFY (not_x1) = NOT(XOTA) — opposite edge

Phase relationships

These five facts carry most of the book's edge reasoning:

• ALET rising = ck1_ck2 rising (in phase, not inverted). The XTAL pad inverts once (clk_in_n = NOT(ck1_ck2)); the ANOS/AVET feedback pair restores ATAL to crystal phase; four more inversions through AZOF → ZAXY → ZEME → ALET land in phase at 16.3 ge total delay. ADEH = NOT(ATAL) pairs with ATAL in the CPU phase-generator ring.
• ALET and MYVO = NOT(ALET) are complementary clocks at the 4 MHz master rate. ALET is 16.3 ge deep from the crystal; MYVO is 22.2 ge deep (5.9 ge additional from the inverter and wire routing). DFFs clocked by ALET capture on one edge; DFFs clocked by MYVO capture on the opposite edge. This pair drives most per-dot PPU timing.
• TALU and SONO are complementary clocks at 1 MHz (derived from VENA), driving line-level timing.
• WUVU and VENA are toggle DFFs (internal ~Q → D feedback) forming the video clock divider chain. WOSU is a sampler DFF (D input = WUVU) that captures WUVU on XYFY rising to produce a phase-differentiated replica for the LCD-control decode.
• All PPU dividers are held at 0 while VID_RST is asserted (LCD off) and count from zero on deassertion — see Register writes for the deassertion path.

PPU clock domains

Every registered cell in the PPU is clocked by a signal traceable to the crystal. The major clock domains:

Complementary pairs and pipeline relationships

A DFF clocked by A feeding a DFF clocked by NOT(A) forms a half-period pipeline: the downstream cell captures, half a period later, what the upstream cell just captured. Three pairs recur:

Worked through for ALET/MYVO: on ALET rising, the ALET-clocked DFFs (NYKA, LYZU, PYGO, RENE, DOBA, NOPA) capture. On ALET falling — MYVO rising — PORY captures NYKA's new output. PORY therefore always holds the value NYKA captured half a dot earlier.

XUPY-clocked DFFs capture on ALET falling — the opposite edge from the ALET-clocked group. The chain: XOTA is ALET's complement; XOTA clocks WUVU; XUPY = WUVU.q. So BYBA — the scan-done capture (OAM scan) — moves half a dot before DOBA, its ALET-clocked partner in the AVAP edge detector.

TALU / ck1_ck2 half-edge alignment

TALU rises align with ck1_ck2 falling edges (modulo divider-startup phase): WUVU toggles on XOTA↑ = ALET↓ = ck1_ck2↓, VENA captures the toggle on the same edge family, and TALU inverts VENA — so each TALU↑ traces to a ck1_ck2↓ through the divider chain's buffer delays. Measured directly: TALU↑ lands 9,350 ps after its ck1_ck2↓ edge, constant across 51,489 edges (dmg-sim measurement).

Steady-state TALU↑ vs CLK9↑ within one M-cycle

The TALU↑ that opens an M-cycle (clocking NYPE, SAXO, and ROPO) leads the CLK9↑ that opens the same M-cycle (Interrupt dispatch) by 121,110 ps ≈ 0.496 dots (dmg-sim measurement, constant across 51,489 M-cycles). The half-dot offset is structural: the TALU edge comes from the ck1_ck2↓ preceding the boundary (+9,350 ps), the CLK9 edge from T1's ck1_ck2↑ (+8,440 ps): ½ dot − 9,350 + 8,440 = 121,090 ps, matching the measured value to within the edge-asymmetry residual.

The practical reading: "TALU↑ at the M-cycle boundary" fires roughly half a dot before that M-cycle's CLK9↑. The two edges open the same M-cycle but are not co-located.