CH1/CH2: Pulse Channels

The square channels generate tone with two counters. An 11-bit period divider overflows every 0x800 − period ticks. A 3-bit duty step counter advances once per overflow. The behavioural surface is Pan Docs territory; what the netlist supplies is the load network that makes the trigger quirks fall out. The netlist also supplies the exact silicon meaning of "the low two bits of the frequency timer are not modified".

The period divider

apu_4mhz → prescaler /2 → prescaler /2 → chN_1mhz ─(gated by chN_fdis)→ toggle clock
   (CH1: AJER → CALO;  CH2: ATEP → CEMO)
                ↓
  11-bit divider: 11 × tffnl in three ripple sub-chains (4 + 4 + 3),
  joined by single inverters; all stages share one load enable:
      CH1: epyk = NOR(ch1_frst, ch1_restart) → fume/dega/dako
      CH2: duju = NOR(ch2_frst, ch2_restart) → cogu/erog/gypa

Each divider stage is a toggle-with-load cell: l=1 → q ← d combinationally (level-sensitive); l=0 → toggles on its ripple clock.

The remaining structural facts:

• The divider counts up to 0x7FF; the MSB's fall marks overflow. The one-stage detector (CALA + COMY) produces the one-chN_1mhz-cycle pulse chN_frst that opens the reload.
• Trigger and overflow share the same load net. chN_restart and chN_frst are the two NOR inputs — there is no trigger-only load path.
• The reload is level-sensitive. During the window the divider tracks the period source combinationally. The captured value is whatever the source held when the load fell.

Period sources. CH2 (and CH3) load directly from the latched NRx3/NRx4 bits. CH1 loads from acc_d0..10 — the sweep shadow accumulator. That accumulator has three write paths: the sweep adder's sum (clocked per sweep fire), and async per-bit set/reset from NR13/NR14 writes. A trigger immediately after an NR13/NR14 write therefore loads the just-written period (the async path has settled long before the synchroniser fires).

The reload window, edge by edge

Trigger-vs-overflow on the same edge

When the trigger's synchroniser edge coincides with a would-be overflow, the race resolves at the overflow-capture DFF (COMY). COMY's async reset arrives through DYRU = NOR(apu_reset, ch1_restart, DOKA). That reset asserts ~2 ns after the edge, before any overflow ripple or load-induced MSB fall can reach COMY's clock pin (measured: reset at +1,970 ps, earliest possible clock attempt at +2,830 ps). Across all five sub-cases (divider at 0x7FE, 0x7FF, or lower, period MSB set or clear): no chN_frst pulse, no duty advance. The trigger reloads the divider and opens the channel one cycle later, but the duty step is preserved (dmg-sim measurement, 41 trigger events).

The one distinct case is a trigger landing while an overflow window is already active (COMY=1 from the prior edge). That trigger forces the same chN_frst fall the natural self-clear would have produced. The counter advances once, indistinguishably from the natural path.

A retrigger that merely follows a completed overflow is likewise unremarkable. The divider counts the chN_1mhz ticks between the overflow's reload and chN_restart↑ as it would any interval. That count is period-independent, with no suppression and no extra hold (dmg-sim measurement).

Trigger-to-first-overflow: the load-settle cycle

The divider's toggle clock (GEKU / DOCA) is chN_1mhz gated by chN_fdis, so while the channel is disabled the divider holds its value. A channel-enabling trigger loads the divider (chN_restart↑, above) while chN_fdis is still set. The loaded value is then held one extra chN_1mhz tick, because the divider cannot count until chN_fdis clears. A trigger of an already-running channel (chN_fdis already 0) reloads while the toggle clock is still running. The divider then counts on the next tick, with no extra hold.

The duty step counter

A 3-bit ripple counter clocked by chN_frst falling — the end of each natural-overflow window. Its only reset is apu_reset: triggers, DAC-off, and channel-stop never touch it.

The duty decode:

The capture-on-rise / advance-on-fall split means each overflow plays the pre-advance step.

First-trigger gating, decoded. "Duty clocking is disabled until the first trigger" is implemented one stage upstream. The chN_fdis disable latch (set by DAC-off or apu_reset, cleared one cycle after a trigger) gates the divider's toggle clock. No divider ticks means no overflows and no duty clocks. "The first duty step plays as if it were 0" is the PWM latch. apu_reset resets that latch to 0, and only the first real overflow re-captures it.

Fast retriggers never reset the duty counter. Each trigger reloads the divider before it can overflow, removing the only advance path — the counter starves rather than resetting. It freezes at its pre-loop value. That freeze is Pan Docs' "duty step never advances" with the mechanism made precise.

Post-boot state: the boot chime leaves CH1's duty counter at 2. The DAC is on (NR12 = 0xF3 retained), the running latch is set, and the period divider is mid-count at 0x7F9. Only NR52 clears the duty counter, so it persists into the handoff. CH2 stays at 0. See post-boot state. This post-boot step is the baseline the fast-retrigger staircase below counts up from.

The fast-retrigger phase staircase

A fast-retrigger loop freezes the duty counter at its running value, and which value is a staircase in the trigger phase. While the divider free-runs the counter advances once per overflow. The pinned step is therefore just how many overflows landed before the loop's first reload caught the counter. Each extra overflow interval (0x800 − period ticks) of delay adds +1 step.

The emitted bit is the pre-advance step. DUWO captures on chN_frst↑ and the counter advances on the following chN_frst↓, so a counter pinned at k ≥ 1 plays step k − 1. A counter pinned at 0 has seen no overflow, so the PWM latch still holds its apu_reset 0. The flip is therefore one step past the pattern edge. For the 50% pattern (high at steps 4–7) the emitted bit is 0 for a counter pinned at 0–4. The bit goes high at 5 (measured chN_out 0 → full-scale across 4→5).

The inter-trigger audible window

With trigger spacing longer than the overflow interval, the full chain — overflow → PWM capture → mixer — runs between triggers. Measured across a 7-overflow inter-trigger window (dmg-sim measurement, gambatte duty3_pattern_pos7 ROM): the duty counter walks 0→7. The PWM latch holds 1 through six overflows of the 75% pattern, then captures 0 at the seventh, where counter 6 decodes low. That window produces a sustained ~375 µs audible pulse and then silence. Across that window every digital gate operated exactly as the cell map says, with no hidden muting.

A sweep period change rescales the duty capture cadence

The staircase and audible window above hold the period fixed. CH1's period is the sweep shadow accumulator acc_d. A sweep fire that commits a new acc_d changes the rate at which the emitted duty level updates. DUWO re-samples the duty waveform only at each overflow's chN_frst↑ (The duty step counter above), so level updates are one overflow interval — 0x800 − period ticks — apart. A period change rescales that spacing from the next overflow. The counter goes on climbing. The emitted bit holds its last capture until the new period's first overflow re-samples it. A retrigger before that overflow does not shorten the wait. chN_restart async-clears COMY through DYRU, so the retrigger produces no chN_frst pulse of its own (Trigger-vs-overflow on the same edge above). The retrigger only reloads the divider to the new period, leaving the stale capture in place.

The commit, the overflow that first reloads the new period, and the retrigger never share one chN_1mhz edge. They fall in separate cycles, so they never contend on the divider-load net (EPYK). The commit acts on the duty path purely through the period it sets, and hence the capture cadence.