Lock Boundaries
A CPU write to OAM or VRAM meets a lock that is fully open or fully closed, except when the write's strobe straddles a mode boundary. This page fixes the granularity of a lock change at one M-cycle, and collects the straddle cases at each boundary.
- Both enable chains are stable away from a mode boundary, so the window a CPU write sees is fully open or fully closed.
- A lock transition is M-cycle-quantised: outcomes flip exactly one M-cycle apart (dmg-sim measurement, gbmicrotest families).
- The exception is a straddling write — all three OAM-side straddles are characterised; the VRAM-side one is outside the netlist's scope.
Away from mode boundaries both enable chains are stable, so a CPU write
sees a fully-open or fully-closed window — never a partial one. Outcomes
flip exactly one M-cycle apart across a lock transition (dmg-sim
measurement, gbmicrotest oam_write_l0_* / vram_write_l[01]_*
families).
The exception is a write whose strobe straddles a boundary transition. On the OAM side all three boundaries are characterised in CPU-visible mode boundaries. A Mode 2→3 straddle lands through the ~6.5 ns permit gap. A Mode 3→0 straddle lands the moment the permit opens. Mode 0→2 closes cleanly, so the write is blocked. The VRAM-side straddle reaches the off-chip SRAM as a partial cycle, outside the netlist's scope (VRAM writes; Appendix C).