The Tile Fetcher

The BG/window tile fetcher is a 3-bit counter, a drain-detect pipeline, and a combinational VRAM address generator. It runs continuously through Mode 3, producing one tile (two bitplane bytes) every 8 dots, in parallel with pixel shifting.

The fetch counter

The counter advances through six states (0–5) to drive one tile fetch. It then holds at 5 until the NYXU reset pulse restarts it for the next tile, window handoff, or Mode 3 startup. (The downstream drain-detect pipeline that closes each tile is tabulated in the next section.)

LEBO (nand2) = NAND(MOCE, ALET) — gated clock, stops when MOCE=0
├── LAXU (dffr) [clk=LEBO] — bit 0
│   ├── MESU (dffr) [clk=LAXU.~Q] — bit 1 (ripple)
│   │   └── NYVA (dffr) [clk=MESU.~Q] — bit 2 (ripple)
│   └── data to LYZU
MOCE (nand3) = NAND(LAXU, NYVA, NYXU) — self-stop at count 5 when NYXU=1

Reset and restart. NYXU = NOR3(MOSU, TEVO, AVAP) combines three triggers: window activation (MOSU), tile boundary (TEVO), and OAM-scan completion (AVAP). A single ~0.5-dot NYXU pulse asynchronously resets the counter DFFs and forces MOCE=1, re-enabling LEBO — clear and clock-restart in one operation. At count 5 (LAXU=1, MESU=0, NYVA=1), MOCE freezes LEBO and the counter holds. The six states match the 6 dots of one tile fetch (3 VRAM accesses × 2 dots).

NYXU firings per scanline under normal BG rendering — 22 at SCX=0, 23 at SCX&7 ∈ {1..7}:

The 167-pixel SACU count per Mode 3 is decoupled from the TEVO firings. SACU runs at CLKPIPE cadence, not fetch cadence.

The 8-dot tile cycle

The counter counts 0→5 over 6 dots, then holds at 5 for 2 dots while the cascade (NYKA → PORY → RENE/RYFA) drains. When SEKO detects the drained state, TEVO fires and resets the counter for the next tile. The counter is a position within the current tile fetch, not an absolute Mode 3 position. Fetching and pixel shifting run in parallel. The per-tile TEVO reset is normal fetcher operation, not a stall.

The 2-dot hold, stage by stage:

1. The counter reaches 5. MOCE→0 freezes LEBO, and LYRY→1 starts propagating down the NYKA/PORY/PYGO half-dot pipeline. POKY sets, and RYFA still holds 1.
2. Hold-dot 1: RENE captures RYFA=1 — SEKO stays 0.
3. Hold-dot 2: PANY falls, RYFA captures 0, and RENE follows. Once RYFA and RENE are both 0, SEKO rises, TEVO fires, and NYXU resets the counter. LYRY's fall then propagates back down, returning SEKO to 0.

The cascade does not drain during a sprite fetch. When FEPO=1 freezes SEGU at 1 (the pixel clock), RYFA is frozen at its pre-freeze 1, and RENE keeps re-capturing 1. SEKO therefore never rises, so neither TEVO nor NYXU fires during the sprite window. The counter holds at 5 by the ordinary MOCE self-stop. The reset that would normally come 2 dots later does not arrive until the freeze lifts (sprite pipeline).

Outside Mode 3 the MOSU/TEVO/AVAP cascade is idle, so NYXU=1 and the counter is not held in reset. The counter instead freezes via the self-stop at whatever value was last clocked (typically 5), and holds there until the next AVAP. Reset domains:

• LAXU/MESU/NYVA — reset on every NYXU pulse;
• PYGO/RENE/RYFA/LYZU — the mode3 reset net (held at 0 outside Mode 3);
• NYKA/PORY — NAFY (VID_RST plus window-related events).

The fetch cycle and VRAM addressing

Each tile fetch takes 6 dots:

The set-address/data-arrives pattern assumes the standard async-SRAM model. VRAM is external, so its access time is not determined by the on-die netlist. The address is driven combinationally from the fetch counter through the VRAM address adder. The full carry chain takes up to 66.2 ge, though in practice the high bits settle from the previous line.

LCDC.3/4/6 sampling during the fetch

Three LCDC bits feed the fetcher's VRAM address generation. Each path is purely combinational, gated by tri-state drivers that the fetch counter enables at specific stages:

The enables derive combinationally from the fetch counter:

• BAFY / WUKO (BG vs window tilemap arm) — mutually exclusive, both fire at counter=0.
• bp_cy (the NETA AND2 output) — active across counters 2–5, measured 4.000 dots continuous per fetch. TILE_SEL is therefore read twice per fetch, once per bitplane.
• PYJU (dffr_cc_q) — captures VRAM data bit 7 at the tile-index stage and feeds VUZA, implementing the signed/unsigned tile-index split.

The sampling cadence:

Mid-fetch writes. A CUPA write landing mid-cycle takes effect by stage. A write before the sampling stage takes effect normally. A write during the sampling stage leaves the fetched byte as the one the address held when the access window opened. A write after the sampling stage takes effect on the next fetch. For BG_MAP and WIN_MAP this produces tile-aligned 8-pixel divergence. For TILE_SEL, a write landing between counter=2 and counter=4 produces a hybrid fetch. The low bitplane comes from the old tile-data block, and the high bitplane from the new (the Mealybug m3_lcdc_tile_sel_win_change reference image). Model the hybrid fetch by reading each bitplane once, at its own sample stage.

LCDC.5 transients and the fetcher arbitration

The window-enable consumer chain enters the tilemap-select arbitration through PYNU only. That chain — PYNU → NOCU → PORE → in_window → AXAD/XEZE → BAFY/WUKO — is purely combinational (~3 ge). A mid-Mode-3 LCDC.5 1→0 write therefore switches the fetcher back to BG-tilemap arbitration on the dot the write lands. Every subsequent counter=0 stage then drives ~ma10 from XAFO.

Measured across a 65-dot LCDC.5↓ gap: all 8 counter=0 stages in the gap drive the BG tilemap region, with VEVY tri-stated (high-Z) and AMUV active (dmg-sim measurement, Mealybug m3_lcdc_win_en_change_multiple ROM). That matches the hardware reference image, which shows BG content in the gap.

SCX/SCY sampling during the fetch

SCX and SCY both feed the VRAM address adder, but they enter at different fetch stages. A mid-Mode-3 scroll write therefore splits differently for X and Y:

Like the LCDC fetch-address bits, the scroll address bits are level-sensitive, not edge-captured. Each stage drives the adder from whatever the SCX/SCY latch holds at that stage's address dot (counter=0, then +2, then +4). Which SCY each of the three stages sees therefore depends on where any mid-fetch write commits. A write landing in the counter=2 → counter=4 gap leaves the map row (counter=0) and the low-bitplane fine-Y (counter=2) on the old SCY. The high-bitplane fine-Y (counter=4) takes the new SCY. The two bitplanes therefore split vertically — the Y-direction analogue of the LCDC.4 hybrid fetch.